Patents by Inventor Koichi Kanemoto
Koichi Kanemoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9385072Abstract: Reliability of a semiconductor device is improved. A method of manufacturing a semiconductor device includes a step of arranging a plurality of semiconductor chips next to each other over a chip mounting surface of a die pad. Further, the method of manufacturing a semiconductor device includes a step of electrically coupling the semiconductor chip and the semiconductor chip via a wire. In this regard, a pad (chip-to-chip connection pad) of the semiconductor chip on a second bonding side in the step of coupling the wire is provided such that it is distantly located from a peripheral portion of a surface of the semiconductor chip.Type: GrantFiled: February 4, 2016Date of Patent: July 5, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Koichi Kanemoto
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Publication number: 20160155710Abstract: Reliability of a semiconductor device is improved. A method of manufacturing a semiconductor device includes a step of arranging a plurality of semiconductor chips next to each other over a chip mounting surface of a die pad. Further, the method of manufacturing a semiconductor device includes a step of electrically coupling the semiconductor chip and the semiconductor chip via a wire. In this regard, a pad (chip-to-chip connection pad) of the semiconductor chip on a second bonding side in the step of coupling the wire is provided such that it is distantly located from a peripheral portion of a surface of the semiconductor chip.Type: ApplicationFiled: February 4, 2016Publication date: June 2, 2016Inventor: Koichi KANEMOTO
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Patent number: 9275945Abstract: Reliability of a semiconductor device is improved. A method of manufacturing a semiconductor device includes a step of arranging a plurality of semiconductor chips next to each other over a chip mounting surface of a die pad. Further, the method of manufacturing a semiconductor device includes a step of electrically coupling the semiconductor chip and the semiconductor chip via a wire. In this regard, a pad (chip-to-chip connection pad) of the semiconductor chip on a second bonding side in the step of coupling the wire is provided such that it is distantly located from a peripheral portion of a surface of the semiconductor chip.Type: GrantFiled: April 23, 2014Date of Patent: March 1, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Koichi Kanemoto
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Patent number: 9257371Abstract: A semiconductor device is reduced in size. The semiconductor device includes a die pad, a plurality of leads arranged around the die pad, a memory chip and a power source IC chip mounted over the die pad, a logic chip mounted over the memory chip, a plurality of down bonding wires for connecting the semiconductor chip to the die pad, a plurality of lead wires for connecting the semiconductor chip to leads, and a plurality of inter-chip wires. Further, the logic chip is arranged at the central part of the die pad in a plan view, and the power source IC chip is arranged in a corner part region of the die pad in the plan view. This reduces the size of the QFN.Type: GrantFiled: March 12, 2015Date of Patent: February 9, 2016Assignee: Renesas Electronics CorporationInventors: Chikako Imura, Koichi Kanemoto
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Publication number: 20150187682Abstract: A semiconductor device is reduced in size. The semiconductor device includes a die pad, a plurality of leads arranged around the die pad, a memory chip and a power source IC chip mounted over the die pad, a logic chip mounted over the memory chip, a plurality of down bonding wires for connecting the semiconductor chip to the die pad, a plurality of lead wires for connecting the semiconductor chip to leads, and a plurality of inter-chip wires. Further, the logic chip is arranged at the central part of the die pad in a plan view, and the power source IC chip is arranged in a corner part region of the die pad in the plan view. This reduces the size of the QFN.Type: ApplicationFiled: March 12, 2015Publication date: July 2, 2015Inventors: Chikako IMURA, Koichi KANEMOTO
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Patent number: 8987882Abstract: A semiconductor device is reduced in size. The semiconductor device includes a die pad, a plurality of leads arranged around the die pad, a memory chip and a power source IC chip mounted over the die pad, a logic chip mounted over the memory chip, a plurality of down bonding wires for connecting the semiconductor chip to the die pad, a plurality of lead wires for connecting the semiconductor chip to leads, and a plurality of inter-chip wires. Further, the logic chip is arranged at the central part of the die pad in a plan view, and the power source IC chip is arranged in a corner part region of the die pad in the plan view. This reduces the size of the QFN.Type: GrantFiled: September 3, 2013Date of Patent: March 24, 2015Assignee: Renesas Electronics CorporationInventors: Chikako Imura, Koichi Kanemoto
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Publication number: 20140332942Abstract: Reliability of a semiconductor device is improved. A method of manufacturing a semiconductor device includes a step of arranging a plurality of semiconductor chips next to each other over a chip mounting surface of a die pad. Further, the method of manufacturing a semiconductor device includes a step of electrically coupling the semiconductor chip and the semiconductor chip via a wire. In this regard, a pad (chip-to-chip connection pad) of the semiconductor chip on a second bonding side in the step of coupling the wire is provided such that it is distantly located from a peripheral portion of a surface of the semiconductor chip.Type: ApplicationFiled: April 23, 2014Publication date: November 13, 2014Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Koichi KANEMOTO
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Patent number: 8803303Abstract: In a QFP with a chip-stacked structure in which a lower surface of a die pad is exposed from a lower surface of a sealing member, a semiconductor chip having a BCB film, which is made of a polymeric material containing at least benzocyclobutene in its backbone as an organic monomer and formed on its surface, is mounted at a position (second stage) that is away from the die pad. As a result, even when moisture invades through the interface between the die pad and the sealing member, it is possible to prolong the time required for the moisture to reach the semiconductor chip, and subsequently to make moisture absorption defect less likely to occur.Type: GrantFiled: December 25, 2013Date of Patent: August 12, 2014Assignee: Renesas Electronics CorporationInventor: Koichi Kanemoto
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Publication number: 20140103515Abstract: In a QFP with a chip-stacked structure in which a lower surface of a die pad is exposed from a lower surface of a sealing member, a semiconductor chip having a BCB film, which is made of a polymeric material containing at least benzocyclobutene in its backbone as an organic monomer and formed on its surface, is mounted at a position (second stage) that is away from the die pad. As a result, even when moisture invades through the interface between the die pad and the sealing member, it is possible to prolong the time required for the moisture to reach the semiconductor chip, and subsequently to make moisture absorption defect less likely to occur.Type: ApplicationFiled: December 25, 2013Publication date: April 17, 2014Applicant: Renesas Electronics CorporationInventor: Koichi KANEMOTO
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Publication number: 20140084434Abstract: A semiconductor device is reduced in size. The semiconductor device includes a die pad, a plurality of leads arranged around the die pad, a memory chip and a power source IC chip mounted over the die pad, a logic chip mounted over the memory chip, a plurality of down bonding wires for connecting the semiconductor chip to the die pad, a plurality of lead wires for connecting the semiconductor chip to leads, and a plurality of inter-chip wires. Further, the logic chip is arranged at the central part of the die pad in a plan view, and the power source IC chip is arranged in a corner part region of the die pad in the plan view. This reduces the size of the QFN.Type: ApplicationFiled: September 3, 2013Publication date: March 27, 2014Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Chikako IMURA, Koichi KANEMOTO
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Patent number: 8637966Abstract: In a QFP with a chip-stacked structure in which a lower surface of a die pad is exposed from a lower surface of a sealing member, a semiconductor chip having a BCB film, which is made of a polymeric material containing at least benzocyclobutene in its backbone as an organic monomer and formed on its surface, is mounted at a position (second stage) that is away from the die pad. As a result, even when moisture invades through the interface between the die pad and the sealing member, it is possible to prolong the time required for the moisture to reach the semiconductor chip, and subsequently to make moisture absorption defect less likely to occur.Type: GrantFiled: December 17, 2012Date of Patent: January 28, 2014Assignee: Renesas Electronics CorporationInventor: Koichi Kanemoto
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Patent number: 8518744Abstract: The reliability of the semiconductor device which has the structure which stores a plurality of semiconductor chips with which plane sizes differ in the same sealing body in the state where they are accumulated via the insulating film which has adhesive property is improved. In the semiconductor device which has the structure which stores a plurality of semiconductor chips with which plane sizes differ in the same sealing body in the state where they are accumulated via DAF, thickness of DAF of the back surface of the uppermost semiconductor chip with which the control circuit was formed was made thicker than each of DAF of the back surface of the lower layer semiconductor chip with which the memory circuit was formed. Hereby, the defect that the bonding wire which connects the uppermost semiconductor chip and a wiring substrate contacts the main surface corner part of a lower layer semiconductor chip can be reduced.Type: GrantFiled: March 9, 2011Date of Patent: August 27, 2013Assignee: Renesas Electronics CorporationInventors: Takashi Kikuchi, Koichi Kanemoto, Chuichi Miyazaki, Toshihiro Shiotsuki
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Publication number: 20110159641Abstract: The reliability of the semiconductor device which has the structure which stores a plurality of semiconductor chips with which plane sizes differ in the same sealing body in the state where they are accumulated via the insulating film which has adhesive property is improved. In the semiconductor device which has the structure which stores a plurality of semiconductor chips with which plane sizes differ in the same sealing body in the state where they are accumulated via DAF, thickness of DAF of the back surface of the uppermost semiconductor chip with which the control circuit was formed was made thicker than each of DAF of the back surface of the lower layer semiconductor chip with which the memory circuit was formed. Hereby, the defect that the bonding wire which connects the uppermost semiconductor chip and a wiring substrate contacts the main surface corner part of a lower layer semiconductor chip can be reduced.Type: ApplicationFiled: March 9, 2011Publication date: June 30, 2011Inventors: Takashi KIKUCHI, Koichi KANEMOTO, Chuichi MIYAZAKI, Toshihiro SHIOTSUKI
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Patent number: 7923292Abstract: In the semiconductor device which has the structure which stores a plurality of semiconductor chips with which plane sizes differ in the same sealing body in the state where they are accumulated via DAF, thickness of DAF of the back surface of the uppermost semiconductor chip with which the control circuit was formed was made thicker than each of DAF of the back surface of the lower layer semiconductor chip with which the memory circuit was formed. Hereby, the defect that the bonding wire which connects the uppermost semiconductor chip and a wiring substrate contacts the main surface corner part of a lower layer semiconductor chip can be reduced.Type: GrantFiled: July 29, 2010Date of Patent: April 12, 2011Assignee: Renesas Electronics CorporationInventors: Takashi Kikuchi, Koichi Kanemoto, Chuichi Miyazaki, Toshihiro Shiotsuki
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Publication number: 20100311205Abstract: The reliability of the semiconductor device which has the structure which stores a plurality of semiconductor chips with which plane sizes differ in the same sealing body in the state where they are accumulated via the insulating film which has adhesive property is improved. In the semiconductor device which has the structure which stores a plurality of semiconductor chips with which plane sizes differ in the same sealing body in the state where they are accumulated via DAF, thickness of DAF of the back surface of the uppermost semiconductor chip with which the control circuit was formed was made thicker than each of DAF of the back surface of the lower layer semiconductor chip with which the memory circuit was formed. Hereby, the defect that the bonding wire which connects the uppermost semiconductor chip and a wiring substrate contacts the main surface corner part of a lower layer semiconductor chip can be reduced.Type: ApplicationFiled: July 29, 2010Publication date: December 9, 2010Inventors: Takashi KIKUCHI, Koichi KANEMOTO, Chuichi MIYAZAKI, Toshihiro SHIOTSUKI
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Patent number: 7804176Abstract: This invention is to provide a nonvolatile memory device that enhances a size reduction and mass productivity while ensuring reliability and signal transmission performance. A nonvolatile memory chip having a first side formed with no pads and a second side formed with pads is mounted on a mounting substrate. A control chip for controlling the nonvolatile memory chip is mounted on the nonvolatile memory chip. The control chip has a first pad row corresponding to the pads of the nonvolatile memory chip. The first pad row is mounted adjacent to the first side of the nonvolatile memory chip. The first pad row of the control chip and a first electrode row formed on the mounting substrate are connected via a first wire group. The pads of the nonvolatile memory chip and a second electrode row formed on the mounting substrate are connected via a second wire group. The first electrode row and the second electrode row are connected through wirings formed in the mounting substrate.Type: GrantFiled: January 23, 2007Date of Patent: September 28, 2010Assignee: Renesas Electronics CorporationInventors: Kazuko Hanawa, Takashi Kikuchi, Koichi Kanemoto, Michiaki Sugiyama, Chikako Imura
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Patent number: 7795741Abstract: A semiconductor device which stores a plurality of semiconductor chips, having planar sizes which differ, in the same sealing body in a state in which they are accumulated via an insulating film which has an adhesive property. In the semiconductor device, the thickness of DAF of the back surface of the uppermost semiconductor chip with which the control circuit is formed is thicker than each of DAF of the back surface of the lower layer semiconductor chip with which the memory circuit is formed.Type: GrantFiled: September 7, 2007Date of Patent: September 14, 2010Assignee: Renesas Technology Corp.Inventors: Takashi Kikuchi, Koichi Kanemoto, Chuichi Miyazaki, Toshihiro Shiotsuki
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Publication number: 20080254574Abstract: By preparing a package substrate which has a plurality of lands of NSMD structure, and the output wiring and dummy wiring which were connected to each of the lands, and have been arranged mutually in the location of 180° symmetry, and printing solder by a printing method to the lands after the package assembly, the variation in the height of the solder coat between lands can be reduced, and improvement in the mountability of LGA (semiconductor device) is achieved.Type: ApplicationFiled: June 17, 2008Publication date: October 16, 2008Inventors: Takashi KIKUCHI, Koichi Kanemoto, Michiaki Sugiyama, Hiroshi Kawakukbo
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Publication number: 20080251897Abstract: The reliability of the semiconductor device which has the structure which stores a plurality of semiconductor chips with which plane sizes differ in the same sealing body in the state where they are accumulated via the insulating film which has adhesive property is improved. In the semiconductor device which has the structure which stores a plurality of semiconductor chips with which plane sizes differ in the same sealing body in the state where they are accumulated via DAF, thickness of DAF of the back surface of the uppermost semiconductor chip with which the control circuit was formed was made thicker than each of DAF of the back surface of the lower layer semiconductor chip with which the memory circuit was formed. Hereby, the defect that the bonding wire which connects the uppermost semiconductor chip and a wiring substrate contacts the main surface corner part of a lower layer semiconductor chip can be reduced.Type: ApplicationFiled: September 7, 2007Publication date: October 16, 2008Inventors: Takashi Kikuchi, Koichi Kanemoto, Chuichi Miyazaki, Toshihiro Shiotsuki
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Patent number: 7399694Abstract: By preparing a package substrate which has a plurality of lands of NSMD structure, and the output wiring and dummy wiring which were connected to each of the lands, and have been arranged mutually in location of 180° symmetry, and printing solder by a printing method to the lands after the package assembly, the variation in the height of the solder coat between lands can be reduced, and improvement in the mountability of LGA (semiconductor device) is achieved.Type: GrantFiled: July 10, 2006Date of Patent: July 15, 2008Assignee: Renesas Technology Corp.Inventors: Takashi Kikuchi, Koichi Kanemoto, Michiaki Sugiyama, Hiroshi Kawakukbo