Abstract: A semiconductor structure includes a backside power rail disposed in a backside dielectric layer, and dielectric spacer layers laterally extending inwardly from opposing sidewalls of the backside dielectric layer and on a portion of a bottom surface of the backside power rail.

Abstract: Embodiments of present invention provide a method of forming a MRAM structure. The method includes forming a sacrificial dielectric layer on top of a bottom contact; forming a stack of a first ferromagnetic layer, a tunnel barrier layer, a second ferromagnetic layer, and at least one hard mask on top of the sacrificial dielectric layer; forming an interlevel-dielectric (ILD) layer surrounding the stack; creating one or more via holes in the ILD layer to expose the sacrificial dielectric layer; selectively removing the sacrificial dielectric layer to create an opening underneath the first ferromagnetic layer; filling the opening with a first conductive material to form a bottom electrode; removing the at least one hard mask to expose the second ferromagnetic layer; and forming a top electrode of a second conductive material on top of the second ferromagnetic layer. An MRAM structure formed thereby is also provided.

Abstract: A semiconductor structure includes a shallow trench isolation region disposed within a semiconductor substrate, and a conductive spacer disposed within the shallow trench isolation region.

Abstract: A semiconductor structure is presented including a first level of interconnect wiring, a second level of interconnect wiring disposed above the first level of interconnect wiring, a third level of interconnect wiring disposed above the second level of interconnect wiring, and a skip via extending from the third level of interconnect wiring to the first level of interconnect wiring such that a sidewall of the skip via maintains electrical contact with the second level of interconnect wiring. A contact area between the sidewall of the skip via and the second level of interconnect wiring is greater than a contact area between a bottom portion of the skip via and a top portion of the first level of interconnect wiring.

Abstract: A wire interconnect, a wire interconnect structure, and a method to form wire interconnect structures with locally widened profiles. The wire interconnect may include a first portion of the wire interconnect with a first width. The wire interconnect may also include a second portion of the wire interconnect with a second width, where the second width is greater than the first width, and where the second portion of the wire interconnect is above the first portion of the wire interconnect. The wire interconnect may also include a third portion of the wire interconnect with a third width, where the third width is less than the second width, and where the third portion of the wire interconnect is above the second portion of the wire interconnect.

Abstract: A semiconductor device includes a transistor having a source/drain region and a contact disposed on the source/drain region. The semiconductor device further includes a via extending from the contact along a side of the source/drain region to a power element. The contact and the via each comprise a plurality of conductive materials.

Abstract: A semiconductor structure includes a first via-to-backside power rail having a lower portion and an upper portion. The lower portion is connected to a first backside power rail and has a first width and the upper portion has a second width less than the first width.

Abstract: A first power rail directly below and connected to a source-drain epitaxy region of a positive field effect transistor (p-FET) region, a second power rail directly below and connected to a source-drain epitaxy region of a negative field effect transistor (n-FET) region, the first power rail and the second power rail each comprise vertical side surfaces which taper in an opposite direction from each other. Forming a first power rail by subtractive metal etch, where the first power rail is directly below and connected to a source-drain epitaxy region of a p-FET region and forming a second power rail by damascene process, where the second power rail is directly below and connected to a source-drain epitaxy region of an n-FET region, the first power rail and the second power rail each comprise vertical side surfaces which taper in an opposite direction from each other.

Abstract: An interconnect structure includes a diffusion barrier layer disposed on exterior surfaces of an opening in a dielectric layer. A top surface of the diffusion barrier layer is below a top surface of the opening. A liner layer is disposed on a bottom surface and sidewalls of the diffusion barrier layer. A spacer layer is disposed on the top surface of the diffusion barrier layer and the liner layer and exposed sidewalls of the opening. An interconnect metal is disposed on the liner layer and the spacer layer. A metal cap is disposed on the interconnect metal.

Abstract: Semiconductor devices and methods of making the same include a first lower device and a second lower device on a substrate. A first upper device is over the first lower device and a second upper device is over the second lower device. A first lower contact extends from a height above the first upper device and makes electrical contact with a top surface and a sidewall surface of the first lower device. A second lower contact extends from a height above the second upper device and makes electrical contact with a top surface and a sidewall surface of the second lower device. An insulating barrier is between the first lower contact and the second lower contact.

Abstract: A semiconductor device is provided. The semiconductor device includes a memory including a bottom electrode, a magnetic tunnel junction (MTJ) stack on the bottom electrode, and an upper electrode on the MTJ stack. The semiconductor device also includes at least one dielectric layer formed around the memory, wherein a top metal layer contact hole is formed in the at least one dielectric layer, a dielectric liner layer formed in the top metal contact hole, and a top metal layer contact in the top metal layer contact hole.

Abstract: A semiconductor device comprising a contact comprising a first section and a second section; wherein the first section of the contact is located on a front side of a source or drain; wherein the second section extends from the front side of the source or drain to a backside of the source or drain; wherein the second section of the contact is comprised of a via and a connection area; wherein the via has a first width and the connection area has a second width, and wherein the second width is larger than the first width.

Abstract: A method to form a semiconductor structure for a magnetoresistive random-access memory (MRAM) device where the material for the top electrode and the bottom electrode is deposited in a single process. The method includes conformally depositing an electrode material over a magnetic tunnel junction (MTJ) pillar, under the MTJ pillar, around a spacer encapsulating and extending above the MTJ pillar. The method includes recessing the electrode material to form a thinner portion of the electrode material over the MTJ pillar. The thinner portion of the electrode material forms a thinner portion of the electrode material over the MTJ pillar that is a top electrode. The portion of the electrode material under the MTJ pillar forms a bottom electrode that is thicker than the top electrode.

Abstract: A method of via formation including forming a sacrificial mask over a conductive layer, forming a plurality of pillars in the sacrificial mask and the conductive layer, wherein each pillar of the plurality of pillars includes a sacrificial cap and a first conductive via, depositing a spacer between the plurality of pillars, masking at least one of the sacrificial caps, removing at least one of the sacrificial caps to create openings, forming second conductive vias in the openings, and depositing a dielectric coplanar to a top surface of the second conductive vias.

Abstract: A microelectronics structure including a skip level via extending from an upper level metal line in an upper level of the at least two interlevel dielectric levels through a first an interlevel dielectric level that is on the substrate level without contacting an interlevel metal line. The skip level via extends into electrical contact with a first element of electrical contact features in a lower level of the at least two interlevel dielectric levels. The skip level via includes a spacer that is present on sidewalls of the skip level via. The structure also includes a single level via, in which the dielectric material of the spacer of the skip level via is not present on the sidewalls of the single level via.

Abstract: A method of forming a pitch pattern is provided. The method includes forming two adjacent mandrels separated by a first distance, D1, on a substrate, and forming a first set of alternating sidewall spacers between the two adjacent mandrels. The method further includes removing the two adjacent mandrels, and forming a second set of alternating sidewall spacers and a third set of alternating sidewall spacers on opposite sides of the first set of sidewall spacers.

Abstract: A back side contact structure is provided that directly connects a first electrode of a MRAM, which is present in a back side of a wafer, to a source/drain structure of a transistor. The back side contact is self-aligned to the source/drain structure of the transistor as well as to the first electrode of the MRAM. The close proximity between the MRAM and the source/drain structure increases the speed of the device. MRAM yield is not compromised since no re-sputtering of back side contact metal onto the MRAM occurs.

Abstract: A substrative patterning process is provided that forms an interconnect structure including a connector tab located between two adjacent electrically conductive line structures. The connector tab and the two adjacent electrically conductive line structures are of unitary construction and are located in a same metallization level.

Abstract: A method of forming a mandrel for use in a pitch doubling process is provided in which a metal hard mask is inserted between a mandrel material layer and a soft mask. The insertion of the metal hard mask allows for easier pattern transfer into the mandrel material layer and avoids many issues encountered during multi-patterning steps. The insertion of the metal hard mask forms a square mandrel that has a flat top due to durability against etch and ability to wet strip the metal hard mask. The metal hard mask can be tuned before pattern transfer into the underlying mandrel material layer to provide a hard mask pattern that is smaller or larger than the pattern without performing such tuning. The method also can be used to protect the downstream non-mandrel processes where selectivity is crucial.

Abstract: A memory device includes a magnetic tunnel junction (MTJ) pillar between a top electrode and a bottom electrode. An amorphous dielectric hardmask is in contact with a first portion of an uppermost surface of the MTJ pillar. A first portion of a metal layer is disposed on opposite sidewalls of the amorphous dielectric hardmask and in contact with a second portion of the uppermost surface of the MTJ pillar extending outwards from the amorphous dielectric hardmask for providing the top electrode. A dielectric underlayer is in contact with a first portion of a bottommost surface of the MTJ pillar, while a second portion of the metal layer is disposed on opposite sidewalls of the dielectric underlayer. The second portion of the metal layer is in contact with a second portion of the bottommost surface of the MTJ pillar extending outwards from the dielectric underlayer for providing the bottom electrode.