Patents by Inventor Koichi Motoyama

Koichi Motoyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10269698
    Abstract: A structure is provided that includes a lower interconnect level that includes a first interconnect dielectric material layer having an opening that contains a first bimetallization interconnect structure. An upper interconnect level is located above the lower interconnect level. The upper interconnect level includes a second interconnect dielectric material layer having a combined via/line opening, wherein the line portion of the combined via/line opening contains a second bimetallization interconnect structure.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: April 23, 2019
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Oscar van der Straten, Praneet Adusumilli, Koichi Motoyama
  • Patent number: 10217664
    Abstract: A method for forming conductive structures for a semiconductor device includes depositing a reflow liner on walls of trenches formed in a dielectric layer and depositing a reflow material on the reflow liner. The reflow material is reflowed to collect in a lower portion of the trenches. The depositing and the reflowing steps are repeated until the trenches are aggregately filled with the reflow material. The reflow material is planarized to form conductive structures in the trenches.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: February 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lawrence A. Clevenger, Su Chen Fan, Huai Huang, Koichi Motoyama, Wei Wang, Chih-Chao Yang
  • Patent number: 10211101
    Abstract: A method for forming conductive structures for a semiconductor device includes depositing a reflow liner on walls of trenches formed in a dielectric layer and depositing a reflow material on the reflow liner. The reflow material is reflowed to collect in a lower portion of the trenches. The depositing and the reflowing steps are repeated until the trenches are aggregately filled with the reflow material. The reflow material is planarized to form conductive structures in the trenches.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: February 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Lawrence A. Clevenger, Su Chen Fan, Huai Huang, Koichi Motoyama, Wei Wang, Chih-Chao Yang
  • Patent number: 10204828
    Abstract: A method for forming a semiconductor structure using first and second conductive materials, and having first and second trenches with first and second critical dimensions. The second conductive material exhibits a lower resistivity than the first conductive material at a film thickness corresponding to the second critical dimension and the second conductive material exhibits a higher resistivity than the first conductive material at a film thickness corresponding to the first critical dimension. An initial semiconductor structure has the first trench having the first critical dimension and the second trench having the second critical dimension. The second critical dimension is larger than the first critical dimension. A first conductive structure made from one of the first and second conductive materials is formed in the first trench. A second conductive structure made from another of the first and second conductive materials is formed in the second trench.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: February 12, 2019
    Assignee: International Business Machines Corporation
    Inventors: Ruqiang Bao, Benjamin D. Briggs, Lawrence A. Clevenger, Koichi Motoyama, Cornelius Brown Peethala, Michael Rizzolo, Gen Tsutsui
  • Patent number: 10134674
    Abstract: A method of fabricating a metallization layer of a semiconductor device in which copper is used for an interconnect material and cobalt is used to encapsulate the copper. A material is introduced that will interact with the cobalt to cause a hexagonal-close-packed (HCP) crystal structure of cobalt to change to a face-centered-cubic (FCC) crystal structure of cobalt, the FCC crystal structure providing a resistance of the cobalt to migrate.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: November 20, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin David Briggs, James J. Kelly, Koichi Motoyama, Roger Allan Quon, Michael Rizzolo, Theodorus Eduardus Standaert
  • Publication number: 20180277433
    Abstract: A method for forming conductive structures for a semiconductor device includes depositing a reflow liner on walls of trenches formed in a dielectric layer and depositing a reflow material on the reflow liner. The reflow material is reflowed to collect in a lower portion of the trenches. The depositing and the reflowing steps are repeated until the trenches are aggregately filled with the reflow material. The reflow material is planarized to form conductive structures in the trenches.
    Type: Application
    Filed: March 1, 2018
    Publication date: September 27, 2018
    Inventors: Lawrence A. Clevenger, Su Chen Fan, Huai Huang, Koichi Motoyama, Wei Wang, Chih-Chao Yang
  • Publication number: 20180277432
    Abstract: A method for forming conductive structures for a semiconductor device includes depositing a reflow liner on walls of trenches formed in a dielectric layer and depositing a reflow material on the reflow liner. The reflow material is reflowed to collect in a lower portion of the trenches. The depositing and the reflowing steps are repeated until the trenches are aggregately filled with the reflow material. The reflow material is planarized to form conductive structures in the trenches.
    Type: Application
    Filed: November 15, 2017
    Publication date: September 27, 2018
    Inventors: Lawrence A. Clevenger, Su Chen Fan, Huai Huang, Koichi Motoyama, Wei Wang, Chih-Chao Yang
  • Patent number: 9966305
    Abstract: A method for forming an ion flow barrier between conductors includes forming a barrier material through a via in an interlevel dielectric layer and onto a first metal layer and recessing the barrier material to form a thickness of the barrier material on the first metal layer in the via, the thickness forming an ion flow barrier. A second metal layer is deposited in the via over the ion flow barrier such that, during operation, the ion flow barrier reduces ion flow between the first metal layer and the second metal layer while maintaining low resistance.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: May 8, 2018
    Assignee: International Business Machines Corporation
    Inventors: James J. Demarest, James J. Kelly, Koichi Motoyama, Christopher J. Penny, Oscar van der Straten
  • Patent number: 9960078
    Abstract: A method for forming conductive structures for a semiconductor device includes depositing a reflow liner on walls of trenches formed in a dielectric layer and depositing a reflow material on the reflow liner. The reflow material is reflowed to collect in a lower portion of the trenches. The depositing and the reflowing steps are repeated until the trenches are aggregately filled with the reflow material. The reflow material is planarized to form conductive structures in the trenches.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: May 1, 2018
    Assignee: International Business Machines Corporation
    Inventors: Lawrence A. Clevenger, Su Chen Fan, Huai Huang, Koichi Motoyama, Wei Wang, Chih-Chao Yang
  • Publication number: 20180005953
    Abstract: A method of fabricating a metallization layer of a semiconductor device in which copper is used for an interconnect material and cobalt is used to encapsulate the copper. A material is introduced that will interact with the cobalt to cause a hexagonal-close-packed (HCP) crystal structure of cobalt to change to a face-centered-cubic (FCC) crystal structure of cobalt, the FCC crystal structure providing a resistance of the cobalt to migrate.
    Type: Application
    Filed: August 14, 2017
    Publication date: January 4, 2018
    Inventors: Benjamin D. Briggs, James J. Kelly, Koichi Motoyama, Roger Allan Quon, Michael Rizzolo, Theodorus Eduardus Standaert
  • Patent number: 9793213
    Abstract: A method for forming an ion flow barrier between conductors includes forming a barrier material through a via in an interlevel dielectric layer and onto a first metal layer and recessing the barrier material to form a thickness of the barrier material on the first metal layer in the via, the thickness forming an ion flow barrier. A second metal layer is deposited in the via over the ion flow barrier such that, during operation, the ion flow barrier reduces ion flow between the first metal layer and the second metal layer while maintaining low resistance.
    Type: Grant
    Filed: February 16, 2016
    Date of Patent: October 17, 2017
    Assignee: International Business Machines Corporation
    Inventors: James J. Demarest, James J. Kelly, Koichi Motoyama, Christopher J. Penny, Oscar van der Straten
  • Patent number: 9780035
    Abstract: A method for fabricating a metallization layer of a semiconductor device, in which copper is used for an interconnect material and cobalt is used to encapsulate the copper, includes introducing a material that will form an alloy with cobalt and resist a degradation of an effect of the cobalt on encapsulating the copper.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: October 3, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin David Briggs, James J. Kelly, Koichi Motoyama, Roger Allan Quon, Michael Rizzolo, Theodorus Eduardus Standaert
  • Publication number: 20170278939
    Abstract: Source/drain contact structures that exhibit low contact resistance and improved electromigration properties are provided. After forming a first contact conductor portion comprising a metal having a high resistance to electromigration such as tungsten at a bottom portion of source/drain contact trench to form direct contact with a source/drain region of a field effect transistor, a second contact conductor portion comprising a highly conductive metal such as copper or a copper alloy is formed over the first contact conductor portion.
    Type: Application
    Filed: June 12, 2017
    Publication date: September 28, 2017
    Inventors: Praneet Adusumilli, Hemanth Jagannathan, Koichi Motoyama, Oscar Van Der Straten
  • Publication number: 20170243947
    Abstract: Source/drain contact structures that exhibit low contact resistance and improved electromigration properties are provided. After forming a first contact conductor portion comprising a metal having a high resistance to electromigration such as tungsten at a bottom portion of source/drain contact trench to form direct contact with a source/drain region of a field effect transistor, a second contact conductor portion comprising a highly conductive metal such as copper or a copper alloy is formed over the first contact conductor portion.
    Type: Application
    Filed: February 24, 2016
    Publication date: August 24, 2017
    Inventors: Praneet Adusumilli, Hemanth Jagannathan, Koichi Motoyama, Oscar Van Der Straten
  • Patent number: 9741812
    Abstract: Source/drain contact structures that exhibit low contact resistance and improved electromigration properties are provided. After forming a first contact conductor portion comprising a metal having a high resistance to electromigration such as tungsten at a bottom portion of source/drain contact trench to form direct contact with a source/drain region of a field effect transistor, a second contact conductor portion comprising a highly conductive metal such as copper or a copper alloy is formed over the first contact conductor portion.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: August 22, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Praneet Adusumilli, Hemanth Jagannathan, Koichi Motoyama, Oscar Van Der Straten
  • Publication number: 20170236784
    Abstract: A method for forming an ion flow barrier between conductors includes forming a barrier material through a via in an interlevel dielectric layer and onto a first metal layer and recessing the barrier material to form a thickness of the barrier material on the first metal layer in the via, the thickness forming an ion flow barrier. A second metal layer is deposited in the via over the ion flow barrier such that, during operation, the ion flow barrier reduces ion flow between the first metal layer and the second metal layer while maintaining low resistance.
    Type: Application
    Filed: February 16, 2016
    Publication date: August 17, 2017
    Inventors: James J. Demarest, James J. Kelly, Koichi Motoyama, Christopher J. Penny, Oscar van der Straten
  • Publication number: 20170236748
    Abstract: A method for forming an ion flow barrier between conductors includes forming a barrier material through a via in an interlevel dielectric layer and onto a first metal layer and recessing the barrier material to form a thickness of the barrier material on the first metal layer in the via, the thickness forming an ion flow barrier. A second metal layer is deposited in the via over the ion flow barrier such that, during operation, the ion flow barrier reduces ion flow between the first metal layer and the second metal layer while maintaining low resistance.
    Type: Application
    Filed: November 1, 2016
    Publication date: August 17, 2017
    Inventors: James J. Demarest, James J. Kelly, Koichi Motoyama, Christopher J. Penny, Oscar van der Straten
  • Patent number: 9418934
    Abstract: After forming a trench opening including narrow trench portions spaced apart by wide trench portions and forming a stack of a first diffusion barrier layer and a first liner layer on sidewalls and a bottom surface of the trench opening, a reflow process is performed to fill the narrow trench portions but not the wide trench portions with a first conductive material layer. A stack of a second diffusion barrier layer and a second liner layer is formed on portions of the first liner layer and ends of the first conductive material layer exposed by the wide trench portions. A second conductive material layer is deposited to fill the wide trench portions. Portions of the second diffusion barrier layer and the second liner layer located between the first conductive material layer and the second conductive material layer act as vertical blocking boundaries to prevent the electromigration of metal atoms.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: August 16, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Koichi Motoyama, Michael Rizzolo
  • Patent number: 9111938
    Abstract: A structure having a diffusion barrier positioned adjacent to a sidewall and a bottom of an opening being etched in a layer of dielectric material. The structure also having a metal liner positioned directly on top of the diffusion barrier, a seed layer positioned directly on top of the metal liner, wherein the seed layer is made from a material comprising copper, a copper material positioned directly on top of the seed layer, a metallic cap positioned directly on top of and selective to the copper material, and a capping layer positioned directly on top of and adjacent to the metallic cap.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: August 18, 2015
    Assignees: International Business Machines Corporation, GLOBALFOUNDRIES, INC., Renesas Electronics Corporation, STMICROELECTRONICS, INC.
    Inventors: Frieder H. Baumann, Tibor Bolom, Chao-Kun Hu, Koichi Motoyama, Chengyu Niu, Andrew H. Simon
  • Patent number: 9059176
    Abstract: A structure having a diffusion barrier positioned adjacent to a sidewall and a bottom of an opening being etched in a layer of dielectric material. The structure also having a metal liner positioned directly on top of the diffusion barrier, a seed layer positioned directly on top of the metal liner, wherein the seed layer is made from a material comprising copper, a copper material positioned directly on top of the seed layer, a metallic cap positioned directly on top of and selective to the copper material, and a capping layer positioned directly on top of and adjacent to the metallic cap.
    Type: Grant
    Filed: April 20, 2012
    Date of Patent: June 16, 2015
    Assignees: International Business Machines Corporation, STMICROELECTRONICS, INC., Renesas Electronics Corporation, GLOBALFOUNDRIES, INC.
    Inventors: Frieder Hainrich Baumann, Chao-Kun Hu, Andrew H. Simon, Tibor Bolom, Koichi Motoyama, Chengyu Charles Niu