Patents by Inventor Koichi Ohto

Koichi Ohto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8749058
    Abstract: The semiconductor device includes an interlayer insulating film, a wiring provided in the interlayer insulating film, and a SiN film provided over the interlayer insulating film and over the wiring. The peak positions of Si—N bonds of the SiN film, which are measured by FTIR, are within the range of 845 cm?1 to 860 cm?1. This makes it possible to inhibit current leakage in a silicon nitride film, which is a barrier insulating film for preventing the diffusion of wiring metal.
    Type: Grant
    Filed: December 13, 2011
    Date of Patent: June 10, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Tatsuya Usami, Hideaki Tsuchiya, Yukio Miura, Tomoyuki Nakamura, Koichi Ohto, Chikako Ohto, Shinji Yokogawa
  • Patent number: 8642467
    Abstract: In a semiconductor device, an insulating interlayer having a groove is formed on an insulating underlayer. A silicon-diffused metal layer including no metal silicide is buried in the groove. A metal diffusion barrier layer is formed on the silicon-diffused metal layer and the insulating interlayer.
    Type: Grant
    Filed: January 11, 2012
    Date of Patent: February 4, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Koichi Ohto, Toshiyuki Takewaki, Tatsuya Usami, Nobuyuki Yamanishi
  • Patent number: 8486836
    Abstract: A semiconductor device including: a substrate; an insulating film formed over the substrate; a copper interconnect, having a plurality of hillocks formed over the surface thereof, buried in the insulating film; a first insulating interlayer formed over the insulating film and the copper interconnect; a second insulating interlayer formed over the first insulating interlayer; and an electroconductive layer formed over the second insulating interlayer, wherein the top surface of at least one hillock highest of all hillocks is brought into contact with the lower surface of the second insulating interlayer is provided.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: July 16, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Daisuke Oshida, Toshiyuki Takewaki, Takuji Onuma, Koichi Ohto
  • Patent number: 8435828
    Abstract: A method of manufacturing a semiconductor device includes forming a first insulating film over an underlying film by plasma polymerization of cyclic siloxane, and forming a second insulating film on the first insulating film by plasma polymerization of the cyclic siloxane continuously, after forming the first insulating film. The deposition rate of the first insulating film is slower than the deposition rate of the second insulating film.
    Type: Grant
    Filed: January 13, 2011
    Date of Patent: May 7, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Hironori Yamamoto, Yoshihiro Hayashi, Jun Kawahara, Tatsuya Usami, Koichi Ohto
  • Publication number: 20120181694
    Abstract: The semiconductor device includes an interlayer insulating film, a wiring provided in the interlayer insulating film, and a SiN film provided over the interlayer insulating film and over the wiring. The peak positions of Si—N bonds of the SiN film, which are measured by FTIR, are within the range of 845 cm?1 to 860 cm?1. This makes it possible to inhibit current leakage in a silicon nitride film, which is a barrier insulating film for preventing the diffusion of wiring metal.
    Type: Application
    Filed: December 13, 2011
    Publication date: July 19, 2012
    Applicant: Renesas Electronics Corporation
    Inventors: Tatsuya Usami, Hideaki Tsuchiya, Yukio Miura, Tomoyuki Nakamura, Koichi Ohto, Chikako Ohto, Shinji Yokogawa
  • Publication number: 20120108060
    Abstract: In a semiconductor device, an insulating interlayer having a groove is formed on an insulating underlayer. A silicon-diffused metal layer including no metal silicide is buried in the groove. A metal diffusion barrier layer is formed on the silicon-diffused metal layer and the insulating interlayer.
    Type: Application
    Filed: January 11, 2012
    Publication date: May 3, 2012
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Koichi OHTO, Toshiyuki TAKEWAKI, Tatsuya USAMI, Nobuyuki YAMANISHI
  • Patent number: 8115318
    Abstract: In a semiconductor device, an insulating interlayer having a groove is formed on an insulating underlayer. A silicon-diffused metal layer including no metal silicide is buried in the groove. A metal diffusion barrier layer is formed on the silicon-diffused metal layer and the insulating interlayer.
    Type: Grant
    Filed: May 4, 2010
    Date of Patent: February 14, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Koichi Ohto, Toshiyuki Takewaki, Tatsuya Usami, Nobuyuki Yamanishi
  • Publication number: 20110318900
    Abstract: A semiconductor device including: a substrate; an insulating film formed over the substrate; a copper interconnect, having a plurality of hillocks formed over the surface thereof, buried in the insulating film; a first insulating interlayer formed over the insulating film and the copper interconnect; a second insulating interlayer formed over the first insulating interlayer; and an electroconductive layer formed over the second insulating interlayer, wherein the top surface of at least one hillock highest of all hillocks is brought into contact with the lower surface of the second insulating interlayer is provided.
    Type: Application
    Filed: September 8, 2011
    Publication date: December 29, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Daisuke OSHIDA, Toshiyuki TAKEWAKI, Takuji ONUMA, Koichi OHTO
  • Patent number: 8030737
    Abstract: A semiconductor device including: a substrate; an insulating film formed over the substrate; a copper interconnect, having a plurality of hillocks formed over the surface thereof, buried in the insulating film; a first insulating interlayer formed over the insulating film and the copper interconnect; a second insulating interlayer formed over the first insulating interlayer; and an electroconductive layer formed over the second insulating interlayer, wherein the top surface of at least one hillock highest of all hillocks is brought into contact with the lower surface of the second insulating interlayer is provided.
    Type: Grant
    Filed: January 10, 2008
    Date of Patent: October 4, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Daisuke Oshida, Toshiyuki Takewaki, Takuji Onuma, Koichi Ohto
  • Publication number: 20110171775
    Abstract: A method of manufacturing a semiconductor device includes forming a first insulating film over an underlying film by plasma polymerization of cyclic siloxane, and forming a second insulating film on the first insulating film by plasma polymerization of the cyclic siloxane continuously, after forming the first insulating film. The deposition rate of the first insulating film is slower than the deposition rate of the second insulating film.
    Type: Application
    Filed: January 13, 2011
    Publication date: July 14, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Hironori YAMAMOTO, Yoshihiro HAYASHI, Jun KAWAHARA, Tatsuya USAMI, Koichi OHTO
  • Patent number: 7910474
    Abstract: An object of the present invention is to provide a semiconductor device which comprises a barrier film having a high etching selection ratio of the interlayer insulating film thereto, a good preventive function against the Cu diffusion, a low dielectric constant and excellent adhesiveness to the Cu interconnection and a manufacturing method thereof.
    Type: Grant
    Filed: April 4, 2008
    Date of Patent: March 22, 2011
    Assignees: NEC Corporation, Renesas Electronics Corporation
    Inventors: Tatsuya Usami, Noboru Morita, Koichi Ohto, Kazuhiko Endo
  • Patent number: 7897475
    Abstract: A method of forming a semiconductor device, includes forming a lower electrode including a metal and a nitrogen on a semiconductor substrate, irradiating a reducing gas to a surface of the lower electrode, and irradiating a gas containing silicon to the surface of the lower electrode to form a projection containing silicide by reacting the metal with the silicon in an island shape on the surface of the lower electrode. Then, a capacitor film is formed on the lower electrode and the projection, and an upper electrode is formed on the capacitor film.
    Type: Grant
    Filed: March 6, 2008
    Date of Patent: March 1, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Daisuke Oshida, Toshiyuki Takewaki, Takuji Onuma, Koichi Ohto
  • Patent number: 7842602
    Abstract: In a semiconductor device, an insulating interlayer having a groove is formed on an insulating underlayer. A silicon-diffused metal layer including no metal silicide is buried in the groove. A metal diffusion barrier layer is formed on the silicon-diffused metal layer and the insulating interlayer.
    Type: Grant
    Filed: May 17, 2007
    Date of Patent: November 30, 2010
    Assignee: Renesas Electronics Corporation
    Inventors: Koichi Ohto, Toshiyuki Takewaki, Tatsuya Usami, Nobuyuki Yamanishi
  • Patent number: 7833901
    Abstract: In a method of manufacturing a semiconductor device where at least one insulating layer structure having a metal wiring constitution is formed to thereby construct a multi-layered wiring arrangement, a first SiOCH layer is produced. Then, a surface section of the first SiOCH layer is treated to change the surface section of the first SiOCH layer to a second SiOCH layer which features a carbon (C) density lower than that of the first SiOCH layer, a hydrogen (H) density lower than that of the first SiOCH layer and an oxygen (O) density higher than that of the first SiOCH layer. Finally, a silicon dioxide (SiO2) layer is formed on the second SiOCH layer.
    Type: Grant
    Filed: November 2, 2006
    Date of Patent: November 16, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Koichi Ohto, Tatsuya Usami, Noboru Morita, Sadayuki Ohnishi, Koji Arita, Ryohei Kitao, Yoichi Sasaki
  • Publication number: 20100224995
    Abstract: In a semiconductor device, an insulating interlayer having a groove is formed on an insulating underlayer. A silicon-diffused metal layer including no metal silicide is buried in the groove. A metal diffusion barrier layer is formed on the silicon-diffused metal layer and the insulating interlayer.
    Type: Application
    Filed: May 4, 2010
    Publication date: September 9, 2010
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Koichi Ohto, Toshiyuki Takewaki, Tatsuya Usami, Nobuyuki Yamanishi
  • Patent number: 7763979
    Abstract: The dielectric constants of SiC and SiCN that are currently the subjects of much investigation are both 4.5 to 5 or so and that of SiOC, 2.8 to 3.0 or so. With further miniaturization of the interconnection size and the spacing of interconnections brought about by the reduction in device size, there have arisen strong demands that dielectric constants should be further reduced. Furthermore, because the etching selection ratio of SiOC to SiCN as well as that of SiOC to SiC are small, if SiCN or SiC is used as the etching stopper film, the surface of the metal interconnection layer may be oxidized at the time of photoresist removal, which gives rise to a problem of high contact resistance.
    Type: Grant
    Filed: September 25, 2006
    Date of Patent: July 27, 2010
    Assignees: NEC Electronics Corporation, NEC Corporation
    Inventors: Koichi Ohto, Tatsuya Usami, Noboru Morita, Kazuhiko Endo
  • Patent number: 7745937
    Abstract: A first gas including a silicon-containing compound is introduced into a vacuum chamber, to expose a semiconductor substrate placed in the chamber to the first gas atmosphere (silicon processing step). Then the pressure inside the vacuum chamber is reduced to a level lower than the pressure at the time of starting the silicon processing step (depressurizing step). Thereafter, a second gas including a nitrogen-containing compound is introduced into the vacuum chamber, and the semiconductor substrate is irradiated with the second gas plasma (nitrogen plasma step).
    Type: Grant
    Filed: February 16, 2006
    Date of Patent: June 29, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Tatsuya Usami, Koichi Ohto, Toshiyuki Takewaki
  • Patent number: 7737555
    Abstract: In a semiconductor device, an insulating interlayer having a groove is formed on an insulating underlayer. A silicon-diffused metal layer including no metal silicide is buried in the groove. A metal diffusion barrier layer is formed on the silicon-diffused metal layer and the insulating interlayer.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: June 15, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Koichi Ohto, Toshiyuki Takewaki, Tatsuya Usami, Nobuyuki Yamanishi
  • Patent number: 7687917
    Abstract: In a semiconductor device, an insulating interlayer having a groove is formed on an insulating underlayer. A silicon-diffused metal layer including no metal silicide is buried in the groove. A metal diffusion barrier layer is formed on the silicon-diffused metal layer and the insulating interlayer.
    Type: Grant
    Filed: August 28, 2003
    Date of Patent: March 30, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Koichi Ohto, Toshiyuki Takewaki, Tatsuya Usami, Nobuyuki Yamanishi
  • Patent number: 7649258
    Abstract: Propagation of a crack in a semiconductor device is to be suppressed, thus to protect an element forming region. An interface reinforcing film is provided so as to cover a sidewall of a concave portion that penetrates a SiCN film and a SiOC film formed on a silicon substrate. The interface reinforcing film is integrally and continuously formed with another SiOC film, and includes an air gap.
    Type: Grant
    Filed: August 5, 2005
    Date of Patent: January 19, 2010
    Assignee: Nec Electronics Corporation
    Inventors: Tatsuya Usami, Koichi Ohto