Patents by Inventor Koichi Seko

Koichi Seko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10996594
    Abstract: An endless belt includes either a single-layer body including a layer including an imide resin and conductive particles, or a multilayer body including the layer as an outermost layer. The ratio y/x of the layer is 0.8992 or more and 1.0157 or less, where x [log ?/?] is the common logarithm of the surface resistivity of the outer peripheral surface of the layer measured with a ring probe when a voltage of 100 V is applied to the layer for 3 seconds at a load of 1 kg, and y [log ?·cm] is the common logarithm of the volume resistivity of the layer measured with a ring probe when a voltage of 100 V is applied to the layer for 5 seconds at a load of 1 kg.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: May 4, 2021
    Assignee: FUJI XEROX CO., LTD.
    Inventors: Hiroaki Tanaka, Satoya Sugiura, Daisuke Tanemura, Masato Ono, Masato Furukawa, Shigeru Fukuda, Masayuki Seko, Koichi Matsumoto, Shogo Hayashi, Tomoko Suzuki
  • Patent number: 9219021
    Abstract: A semiconductor device includes a substrate serving as a base and having a surface on which electrodes are provided, a semiconductor chip mounted to the surface of the substrate, a sealing portion sealing the semiconductor chip and the surface of the substrate, first vias each penetrating the sealing portion in a thickness direction of the sealing portion to reach the electrodes on the surface of the substrate, external terminals connected to the first vias, and second vias provided near the semiconductor chip, extending to such a depth that the second vias do not penetrate the sealing portion, and insulated from the substrate and the semiconductor chip.
    Type: Grant
    Filed: December 2, 2014
    Date of Patent: December 22, 2015
    Assignee: Panasonic Corporation
    Inventors: Koichi Seko, Katsumi Otani, Katsuyoshi Matsumoto
  • Publication number: 20150084180
    Abstract: A semiconductor device includes a substrate serving as a base and having a surface on which electrodes are provided, a semiconductor chip mounted to the surface of the substrate, a sealing portion sealing the semiconductor chip and the surface of the substrate, first vias each penetrating the sealing portion in a thickness direction of the sealing portion to reach the electrodes on the surface of the substrate, external terminals connected to the first vias, and second vias provided near the semiconductor chip, extending to such a depth that the second vias do not penetrate the sealing portion, and insulated from the substrate and the semiconductor chip.
    Type: Application
    Filed: December 2, 2014
    Publication date: March 26, 2015
    Inventors: Koichi SEKO, Katsumi OTANI, Katsuyoshi MATSUMOTO
  • Patent number: 8866284
    Abstract: A semiconductor device includes a first extended semiconductor chip including a first semiconductor chip and an extension extending outwardly from a side surface of the first semiconductor chip. The semiconductor device also includes a second semiconductor chip mounted above the first extended semiconductor chip and electrically connected with the first semiconductor chip. The first extended semiconductor chip includes a first extension electrode pad provided above the extension and electrically connected with an electrode of the first semiconductor chip.
    Type: Grant
    Filed: July 10, 2013
    Date of Patent: October 21, 2014
    Assignee: Panasonic Corporation
    Inventors: Shouichi Kobayashi, Hiroaki Suzuki, Kazuhide Uriu, Koichi Seko, Takashi Yui, Kiyomi Hagihara
  • Publication number: 20130299957
    Abstract: A semiconductor device includes a first extended semiconductor chip including a first semiconductor chip and an extension extending outwardly from a side surface of the first semiconductor chip. The semiconductor device also includes a second semiconductor chip mounted above the first extended semiconductor chip and electrically connected with the first semiconductor chip. The first extended semiconductor chip includes a first extension electrode pad provided above the extension and electrically connected with an electrode of the first semiconductor chip.
    Type: Application
    Filed: July 10, 2013
    Publication date: November 14, 2013
    Inventors: SHOUICHI KOBAYASHI, HIROAKI SUZUKI, KAZUHIDE URIU, KOICHI SEKO, TAKASHI YUI, KIYOMI HAGIHARA
  • Publication number: 20110210453
    Abstract: When an electronic system is designed, then if an integrated circuit chip (LSI), a package (PKG), and a printed circuit board (PCB) are designed separately and in parallel, it will be found near the end of the design process that a satisfactory electrical characteristic is not achieved. Therefore, a design procedure of each part (e.g., an LSI, a PKG, a PCB, etc.) is decided, and allocation of resources to a part which is designed with a higher priority is decided, and thereafter, the other parts start to be designed. Therefore, a basic interconnect distribution for a circuit board is calculated based on a prediction function for predicting an interconnect distribution for the circuit board using design information of the circuit board as input data, and is output.
    Type: Application
    Filed: May 13, 2011
    Publication date: September 1, 2011
    Applicant: Panasonic Corporation
    Inventors: Keiichi KUSUMOTO, Shinya Tokunaga, Mitumi Ito, Koichi Seko
  • Publication number: 20110012260
    Abstract: To provide a method of designing a semiconductor integrated circuit with a high workability also in an increase in a scale of an LSI and an enhancement in an integration and designing a semiconductor integrated circuit system in which an unnecessary radiation is reduced and which is excellent in a heat characteristic, a reverse design flow to that in the conventional art is implemented, and a mounting substrate such as a printed-circuit board is first designed and a package substrate for mounting an LSI is designed based on a result of the design of the mounting substrate, and a layout design of the LSI to be mounted on the package substrate is then carried out.
    Type: Application
    Filed: September 28, 2010
    Publication date: January 20, 2011
    Applicant: Panasonic Corporation
    Inventors: Shinya TOKUNAGA, Mitsumi Ito, Nobufusa Iwanishi, Koichi Seko, Hiroaki Suzuki, Hiroyuki Tanaka, Yuichi Nishimura, Kazuhiko Fujimoto
  • Patent number: 7831949
    Abstract: To provide a method of designing a semiconductor integrated circuit with a high workability also in an increase in a scale of an LSI and an enhancement in an integration and designing a semiconductor integrated circuit system in which an unnecessary radiation is reduced and which is excellent in a heat characteristic, a reverse design flow to that in the conventional art is implemented, and a mounting substrate such as a printed-circuit board is first designed and a package substrate for mounting an LSI is designed based on a result of the design of the mounting substrate, and a layout design of the LSI to be mounted on the package substrate is then carried out.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: November 9, 2010
    Assignee: Panasonic Corporation
    Inventors: Shinya Tokunaga, Mitsumi Ito, Nobufusa Iwanishi, Koichi Seko, Hiroaki Suzuki, Hiroyuki Tanaka, Yuichi Nishimura, Kazuhiko Fujimoto
  • Patent number: 7565637
    Abstract: A package design method for a semiconductor device of designing a package including a package substrate provided with a wiring pattern, a chip mounted on the package substrate, and a sealing resin which covers the package substrate and the chip, and the wiring pattern including an external connection terminal and an internal connection terminal connected to the chip, the method comprising: setting an acceptable noise value of the package; designing a package layout on the basis of information on connection between the package substrate and the chip; and performing an optimization on package layout data so that an amount of noises remains within a range which is set beforehand, on the basis of the package layout data obtained in the designing process of the package layout.
    Type: Grant
    Filed: November 3, 2006
    Date of Patent: July 21, 2009
    Assignee: Panasonic Corporation
    Inventors: Koichi Seko, Shinya Tokunaga
  • Publication number: 20080022252
    Abstract: To provide a method of designing a semiconductor integrated circuit with a high workability also in an increase in a scale of an LSI and an enhancement in an integration and designing a semiconductor integrated circuit system in which an unnecessary radiation is reduced and which is excellent in a heat characteristic, a reverse design flow to that in the conventional art is implemented, and a mounting substrate such as a printed-circuit board is first designed and a package substrate for mounting an LSI is designed based on a result of the design of the mounting substrate, and a layout design of the LSI to be mounted on the package substrate is then carried out.
    Type: Application
    Filed: June 28, 2007
    Publication date: January 24, 2008
    Inventors: Shinya Tokunaga, Mitsumi Ito, Nobufusa Iwanishi, Koichi Seko, Hiroaki Suzuki, Hiroyuki Tanaka, Yuichi Nishimura, Kazuhiko Fujimoto
  • Publication number: 20070105271
    Abstract: A package design method for a semiconductor device of designing a package including a package substrate provided with a wiring pattern, a chip mounted on the package substrate, and a sealing resin which covers the package substrate and the chip, and the wiring pattern including an external connection terminal and an internal connection terminal connected to the chip, the method comprising: setting an acceptable noise value of the package; designing a package layout on the basis of information on connection between the package substrate and the chip; and performing an optimization on package layout data so that an amount of noises remains within a range which is set beforehand, on the basis of the package layout data obtained in the designing process of the package layout.
    Type: Application
    Filed: November 3, 2006
    Publication date: May 10, 2007
    Inventors: Koichi Seko, Shinya Tokunaga