Patents by Inventor Koichi Shimazaki

Koichi Shimazaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10504867
    Abstract: A semiconductor device has a bonding pad and a wiring layer formed on an insulating film. The wiring layer is spaced from the bonding pad by a gap. A passivation film covers the bonding pad and the wiring layer and fills the gap. The gap has a width equal to or larger than the thickness of the passivation film, and equal to or smaller than twice a side wall thickness of the passivation film covering a side wall of the wiring layer. The semiconductor device has a high resistance to stress during bonding.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: December 10, 2019
    Assignee: ABLIC Inc.
    Inventor: Koichi Shimazaki
  • Patent number: 10497662
    Abstract: In order to inhibit forming cracks under a pad opening during ball bonding without increasing a chip size, a protective film includes a pad opening that exposes a part of a topmost layer metal film of the chip. A second metal film provided under the pad opening has a ring shape that defines a rectangular opening under the pad opening. The opening edge of the opening in the second metal film extends inwardly beyond the edge of the overlying pad opening. Vias connect the second metal film and the topmost layer metal film, and all of these vias are located outside the pad opening in plan view.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: December 3, 2019
    Assignee: ABLIC Inc.
    Inventors: Tomomitsu Risaki, Shoji Nakanishi, Hitomi Sakurai, Koichi Shimazaki
  • Publication number: 20180294243
    Abstract: In order to inhibit forming cracks under a pad opening during ball bonding without increasing a chip size, a protective film includes a pad opening that exposes a part of a topmost layer metal film. A second metal film provided under the pad opening has a ring shape that defines a rectangular opening under the pad opening. The opening edge of the opening in the second metal film extends inwardly beyond the edge of the overlying pad opening.
    Type: Application
    Filed: January 24, 2018
    Publication date: October 11, 2018
    Inventors: Tomomitsu RISAKI, Shoji NAKANISHI, Hitomi SAKURAI, Koichi SHIMAZAKI
  • Publication number: 20170005024
    Abstract: Provided is a semiconductor device that includes a passivation film thinner than a wiring layer and has a high resistance to a stress caused during bonding. In the semiconductor device, a wiring layer (303) is formed in the vicinity of a bonding pad (301) via a gap (601), a passivation film (401) has a thickness smaller than that of the wiring layer (303) forming the bonding pad (301), and the gap (601) has a width equal to or smaller than twice the passivation film thickness.
    Type: Application
    Filed: June 27, 2016
    Publication date: January 5, 2017
    Inventor: Koichi SHIMAZAKI
  • Patent number: 9397088
    Abstract: In order to provide a semiconductor device having high ESD tolerance, a plurality of source wirings (22) are formed of metal films having the same shape and electrically connect a plurality of sources (12) to a ground voltage wiring (22a), respectively, a plurality of drain wirings (23) are formed of metal films having the same shape and electrically connect a plurality of drains (12) to an input voltage wiring (23a), respectively, and a plurality of gate wirings (21) are formed of metal films having the same shape and electrically connect a plurality of gates (11) to the ground voltage wiring (22a), respectively. Further, a back gate wiring (24) is formed of a metal film and electrically connects a back gate (14) to the ground voltage wiring (22a), and the back gate wiring (24) is separated from the source wiring (22) formed on the source (12).
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: July 19, 2016
    Assignee: SII Semiconductor Corporation
    Inventors: Koichi Shimazaki, Yoshitsugu Hirose
  • Patent number: 9391064
    Abstract: In order to provide a semiconductor device having high ESD tolerance, a semiconductor device (IC) is formed so that: a ground voltage wiring (22a) is electrically connected at one end in a wiring direction thereof to a wiring (22b) extending from a ground voltage pad used for external connection; an input voltage wiring (23a) is electrically connected at one end in a wiring direction thereof to a wiring (23b) extending from an input voltage pad used for external connection; and the one end of the ground voltage wiring (22a) and the one end of the input voltage wiring (23a) are substantially opposed to each other across a center of an NMOS transistor (10).
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: July 12, 2016
    Assignee: SII Semiconductor Corporation
    Inventors: Koichi Shimazaki, Yoshitsugu Hirose
  • Patent number: 9299629
    Abstract: A semiconductor device has a semiconductor substrate provided with a scribe region and an IC region. A first insulating film is disposed on the semiconductor substrate across the scribe region and the IC region. At least one separation groove is provided in the first insulating film in the scribe region. Side walls made of a plug metal film are formed only on respective lateral walls of the separation groove so that the plug metal film on the lateral walls does not extend out of the separation groove and does not exist on an upper surface of the first insulating film. A second insulating film covers at least the side walls formed on the respective lateral walls of the separation groove so that the side walls are disposed under the second insulating film.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: March 29, 2016
    Assignee: SEIKO INSTRUMENTS INC.
    Inventors: Tomomitsu Risaki, Shoji Nakanishi, Koichi Shimazaki
  • Publication number: 20150364464
    Abstract: In order to provide a semiconductor device having high ESD tolerance, a plurality of source wirings (22) are formed of metal films having the same shape and electrically connect a plurality of sources (12) to a ground voltage wiring (22a), respectively, a plurality of drain wirings (23) are formed of metal films having the same shape and electrically connect a plurality of drains (12) to an input voltage wiring (23a), respectively, and a plurality of gate wirings (21) are formed of metal films having the same shape and electrically connect a plurality of gates (11) to the ground voltage wiring (22a), respectively. Further, a back gate wiring (24) is formed of a metal film and electrically connects a back gate (14) to the ground voltage wiring (22a), and the back gate wiring (24) is separated from the source wiring (22) formed on the source (12).
    Type: Application
    Filed: December 20, 2013
    Publication date: December 17, 2015
    Applicant: Seiko Instruments Inc.
    Inventors: Koichi SHIMAZAKI, Yoshitsugu HIROSE
  • Publication number: 20150364465
    Abstract: In order to provide a semiconductor device having high ESD tolerance, a semiconductor device (IC) is formed so that: a ground voltage wiring (22a) is electrically connected at one end in a wiring direction thereof to a wiring (22b) extending from a ground voltage pad used for external connection; an input voltage wiring (23a) is electrically connected at one end in a wiring direction thereof to a wiring (23b) extending from an input voltage pad used for external connection; and the one end of the ground voltage wiring (22a) and the one end of the input voltage wiring (23a) are substantially opposed to each other across a center of an NMOS transistor (10).
    Type: Application
    Filed: December 20, 2013
    Publication date: December 17, 2015
    Inventors: Koichi SHIMAZAKI, Yoshitsugu HIROSE
  • Publication number: 20150162296
    Abstract: In order to inhibit a crack under a pad opening without increasing a chip size, a protective film (6) includes a pad opening (9) that exposes a part of a topmost layer metal film (3). The pad opening (9) is rectangular and square, and has an opening width of d0. A second metal film (2) has an opening under the pad opening (9). The opening is rectangular and square, and has an opening width of d4. A distance between an opening edge of the protective film (6) and an opening edge of the second metal film (2) is d3. The second metal film (2) has a rectangular donut shape, and protrudes to an inner side of the pad opening (9) by the distance d3.
    Type: Application
    Filed: May 21, 2013
    Publication date: June 11, 2015
    Inventors: Tomomitsu Risaki, Shoji Nakanishi, Hitomi Sakurai, Koichi Shimazaki
  • Patent number: 8618606
    Abstract: Provided is a semiconductor device comprising: a PW layer formed at a surface of a semiconductor substrate; an NW layer formed at the surface of the semiconductor substrate to be in contact with the PW layer; a p+ base layer formed at the surface of the semiconductor substrate in the PW layer; an n+ collector layer formed at the surface of the semiconductor substrate in the NW layer; an n+ emitter layer located between the p+ base layer and the n+ collector layer and formed at the surface of the semiconductor substrate in the PW layer; and an n± layer formed between the n+ collector layer and the PW layer to be in contact with the n+ collector layer.
    Type: Grant
    Filed: November 1, 2012
    Date of Patent: December 31, 2013
    Assignee: Seiko Instruments Inc.
    Inventors: Tomomitsu Risaki, Shoji Nakanishi, Koichi Shimazaki
  • Patent number: 8324687
    Abstract: Provided is a semiconductor device comprising: a PW layer formed at a surface of a semiconductor substrate; an NW layer formed at the surface of the semiconductor substrate to be in contact with the PW layer; a p+ base layer formed at the surface of the semiconductor substrate in the PW layer; an n+ collector layer formed at the surface of the semiconductor substrate in the NW layer; an n+ emitter layer located between the p+ base layer and the n+ collector layer and formed at the surface of the semiconductor substrate in the PW layer; and an n± layer formed between the n+ collector layer and the PW layer to be in contact with the n+ collector layer.
    Type: Grant
    Filed: January 28, 2010
    Date of Patent: December 4, 2012
    Assignee: Seiko Instruments Inc.
    Inventors: Tomomitsu Risaki, Shoji Nakanishi, Koichi Shimazaki
  • Publication number: 20120185839
    Abstract: It is provided a program execution method, for executing an application program including at least one processing module. The at least one processing module includes at least one process, and being managed with an identification. The method includes the steps of: determining whether the processing module to be executed needs modification by comparing the identification of a running processing module and the identification of a deployed processing module; determining the identification of the processing module to be executed based on history information, which indicates whether the each process included in the at least one processing module has been executed, and on information indicating a different process between the at least one process included in the running processing module and the at least one process included in the deployed processing module; and calling up the processing module by specifying the identification of the determined processing module.
    Type: Application
    Filed: March 25, 2010
    Publication date: July 19, 2012
    Inventors: Akira Nikaido, Koichi Shimazaki, Naotsugu Toume
  • Publication number: 20110221043
    Abstract: Provided is a semiconductor device suitable for preventing film peeling due to dicing and preventing abnormal discharge. The semiconductor device includes a scribe region (003) and an IC region (004). At least one separation groove (007) is provide in an inter-layer insulating film (002) in the scribe region 003, and a side wall (011) made of a plug metal film is formed on each lateral wall of the separation groove (007). A passivation film is provided to cover at least the side walls (011).
    Type: Application
    Filed: February 28, 2011
    Publication date: September 15, 2011
    Inventors: Tomomitsu Risaki, Shoji Nakanishi, Koichi Shimazaki
  • Publication number: 20100187608
    Abstract: Provided is a semiconductor device comprising: a PW layer formed at a surface of a semiconductor substrate; an NW layer formed at the surface of the semiconductor substrate to be in contact with the PW layer; a p+ base layer formed at the surface of the semiconductor substrate in the PW layer; an n+ collector layer formed at the surface of the semiconductor substrate in the NW layer; an n+ emitter layer located between the p+ base layer and the n+ collector layer and formed at the surface of the semiconductor substrate in the PW layer; and an n± layer formed between the n+ collector layer and the PW layer to be in contact with the n+ collector layer.
    Type: Application
    Filed: January 28, 2010
    Publication date: July 29, 2010
    Inventors: Tomomitsu Risaki, Shoji Nakanishi, Koichi Shimazaki
  • Publication number: 20090172122
    Abstract: Provided is a method of transmitting a message in a business process management system that includes a service execution device providing services and a business process management device.
    Type: Application
    Filed: December 17, 2008
    Publication date: July 2, 2009
    Applicant: Hitachi, Ltd.
    Inventors: Naotsugu Toume, Koichi Shimazaki
  • Patent number: 7380093
    Abstract: The present invention relates to a method for allocating volumes having a suitable physical location relationship based on a method of use of files by applications. When an application management unit receives an application area expansion request, a distribution request table is created based on a preset distribution rule table and a file management table. The distribution rule table includes a flag indicating whether or not files stored on a logical disk for allocation, and existing files, may be stored on the same disk drive. A storage management unit selects, in consideration of the distribution request table, a logical disk having suitable physical attributes from unused logical disks satisfying basic conditions such as requested size and RAID configuration. The selected logical disk is allocated to the application.
    Type: Grant
    Filed: June 28, 2005
    Date of Patent: May 27, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Koichi Shimazaki, Yukio Nakano
  • Publication number: 20060224853
    Abstract: The present invention relates to a method for allocating volumes having a suitable physical location relationship based on a method of use of files by applications. When an application management unit receives an application area expansion request, a distribution request table is created based on a preset distribution rule table and a file management table. The distribution rule table includes a flag indicating whether or not files stored on a logical disk for allocation, and existing files, may be stored on the same disk drive. A storage management unit selects, in consideration of the distribution request table, a logical disk having suitable physical attributes from unused logical disks satisfying basic conditions such as requested size and RAID configuration. The selected logical disk is allocated to the application.
    Type: Application
    Filed: June 28, 2005
    Publication date: October 5, 2006
    Inventors: Koichi Shimazaki, Yukio Nakano
  • Patent number: 6925462
    Abstract: The present invention relates to an optimization method in a database management system having the function of accessing external databases. Conventionally, whether functions contained in a query can be executed in external databases depends on a database management system having the functions, and therefore there has been a problem in that a database utilization method cannot apply to query optimization and query execution performance is reduced. To solve the above problem, a database management system having the function of accessing external databases is provided with an optimization step comprising the steps of: obtaining specification about whether to execute functions in a query in external databases; determining whether data referred to in a query is confined to one database; and determining whether a user specifies that the functions in the query are executed in external databases.
    Type: Grant
    Filed: January 10, 2002
    Date of Patent: August 2, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Norifumi Nishikawa, Shigekazu Inohara, Koichi Shimazaki, Kiyomi Hirohata, Kohsaku Yamahira, Shigetoshi Hayashi
  • Publication number: 20020116373
    Abstract: The present invention relates to an optimization method in a database management system having the function of accessing external databases. Conventionally, whether functions contained in a query can be executed in external databases depends on a database management system having the functions, and therefore there has been a problem in that a database utilization method cannot apply to query optimization and query execution performance is reduced. To solve the above problem, a database management system having the function of accessing external databases is provided with an optimization step comprising the steps of: obtaining specification about whether to execute functions in a query in external databases; determining whether data referred to in a query is confined to one database; and determining whether a user specifies that the functions in the query are executed in external databases.
    Type: Application
    Filed: January 10, 2002
    Publication date: August 22, 2002
    Inventors: Norifumi Nishikawa, Shigekazu Inohara, Koichi Shimazaki, Kiyomi Hirohata, Kohsaku Yamahira, Shigetoshi Hayashi