Patents by Inventor Koichi Toba

Koichi Toba has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140242796
    Abstract: To improve a semiconductor device having a nonvolatile memory. a first MISFET, a second MISFET, and a memory cell are formed, and a stopper film made of a silicon oxide film is formed thereover. Then, over the stopper film, a stress application film made of a silicon nitride film is formed, and the stress application film over the second MISFET and the memory cell is removed. Thereafter, heat treatment is performed to apply a stress to the first MISFET. Thus, a SMT is not applied to each of elements, but is applied selectively. This can reduce the degree of degradation of the second MISFET due to H (hydrogen) in the silicon nitride film forming the stress application film. This can also reduce the degree of degradation of the characteristics of the memory cell due to the H (hydrogen) in the silicon nitride film forming the stress application film.
    Type: Application
    Filed: November 13, 2013
    Publication date: August 28, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Koichi TOBA, Hiraku CHAKIHARA, Yoshiyuki KAWASHIMA, Kentaro SAITO, Takashi HASHIMOTO
  • Publication number: 20140209996
    Abstract: A semiconductor device with a nonvolatile memory is provided which has improved characteristics. The semiconductor device includes a control gate electrode, a memory gate electrode disposed adjacent to the control gate electrode, a first insulating film, and a second insulating film including therein a charge storing portion. Among these components, the memory gate electrode is formed of a silicon film including a first silicon region positioned over the second insulating film, and a second silicon region positioned above the first silicon region. The second silicon region contains p-type impurities, and the concentration of p-type impurities of the first silicon region is lower than that of the p-type impurities of the second silicon region.
    Type: Application
    Filed: April 1, 2014
    Publication date: July 31, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Koichi TOBA, Yasushi ISHII, Hiraku CHAKIHARA, Kota FUNAYAMA, Yoshiyuki KAWASHIMA, Takashi HASHIMOTO
  • Publication number: 20130234289
    Abstract: In connection with a semiconductor device including a capacitor element there is provided a technique capable of improving the reliability of the capacitor element. A capacitor element is formed in an element isolation region formed over a semiconductor substrate. The capacitor element includes a lower electrode and an upper electrode formed over the lower electrode through a capacitor insulating film. Basically, the lower electrode and the upper electrode are formed from polysilicon films and a cobalt silicide film formed over the surfaces of the polysilicon films. End portions of the cobalt silicide film formed over the upper electrode are spaced apart a distance from end portions of the upper electrode. Besides, end portions of the cobalt silicide film formed over the lower electrode are spaced apart a distance from boundaries between the upper electrode and the lower electrode.
    Type: Application
    Filed: April 22, 2013
    Publication date: September 12, 2013
    Applicant: Renesas Electronics Corporation
    Inventors: Yoshiyuki KAWASHIMA, Koichi TOBA, Yasushi ISHII, Toshikazu MATSUI, Takashi HASHIMOTO
  • Patent number: 8530958
    Abstract: A semiconductor device having a non-volatile memory is disclosed, whose disturb defect can be diminished or prevented. A memory cell of the non-volatile memory has a memory gate electrode formed over a main surface of a semiconductor substrate through an insulating film for charge storage. A first side wall is formed on a side face of the memory gate electrode, and at a side face of the first side wall, a second side wall is formed. On an upper surface of an n+-type semiconductor region for source in the memory cell there is formed a silicide layer whose end portion on the memory gate electrode MG side is defined by the second side wall.
    Type: Grant
    Filed: March 5, 2010
    Date of Patent: September 10, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Koichi Toba, Yasushi Ishii, Yoshiyuki Kawashima, Satoru Machida, Munekatsu Nakagawa, Kentaro Saito, Toshikazu Matsui, Takashi Hashimoto, Kosuke Okuyama
  • Patent number: 8497547
    Abstract: Provided is a semiconductor device having, over a semiconductor substrate, a control gate electrode and a memory gate electrode which are adjacent to each other and constitute a nonvolatile memory. The height of the memory gate electrode is lower than the height of the control gate electrode. A metal silicide film is formed over the upper surface of the control gate electrode, but not formed over the upper surface of the memory gate electrode. The memory gate electrode has, over the upper surface thereof, a sidewall insulating film made of silicon oxide. This sidewall insulating film is formed in the same step as that for the formation of respective sidewall insulating films over the sidewalls of the memory gate electrode and the control gate electrode. The present invention makes it possible to improve the production yield and performance of the semiconductor device having a nonvolatile memory.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: July 30, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Koichi Toba, Yasushi Ishii, Yoshiyuki Kawashima, Satoru Machida, Munekatsu Nakagawa, Takashi Hashimoto
  • Patent number: 8431978
    Abstract: In connection with a semiconductor device including a capacitor element there is provided a technique capable of improving the reliability of the capacitor element. A capacitor element is formed in an element isolation region formed over a semiconductor substrate. The capacitor element includes a lower electrode and an upper electrode formed over the lower electrode through a capacitor insulating film. Basically, the lower electrode and the upper electrode are formed from polysilicon films and a cobalt silicide film formed over the surfaces of the polysilicon films. End portions of the cobalt silicide film formed over the upper electrode are spaced apart a distance from end portions of the upper electrode. Besides, end portions of the cobalt silicide film formed over the lower electrode are spaced apart a distance from boundaries between the upper electrode and the lower electrode.
    Type: Grant
    Filed: August 16, 2012
    Date of Patent: April 30, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshiyuki Kawashima, Koichi Toba, Yasushi Ishii, Toshikazu Matsui, Takashi Hashimoto
  • Publication number: 20120313160
    Abstract: Provided is a semiconductor device having, over a semiconductor substrate, a control gate electrode and a memory gate electrode which are adjacent to each other and constitute a nonvolatile memory. The height of the memory gate electrode is lower than the height of the control gate electrode. A metal silicide film is formed over the upper surface of the control gate electrode, but not formed over the upper surface of the memory gate electrode. The memory gate electrode has, over the upper surface thereof, a sidewall insulating film made of silicon oxide. This sidewall insulating film is formed in the same step as that for the formation of respective sidewall insulating films over the sidewalls of the memory gate electrode and the control gate electrode. The present invention makes it possible to improve the production yield and performance of the semiconductor device having a nonvolatile memory.
    Type: Application
    Filed: August 21, 2012
    Publication date: December 13, 2012
    Inventors: Koichi TOBA, Yasushi Ishii, Yoshiyuki Kawashima, Satoru Machida, Munekatsu Nakagawa, Takashi Hashimoto
  • Publication number: 20120306051
    Abstract: In connection with a semiconductor device including a capacitor element there is provided a technique capable of improving the reliability of the capacitor element. A capacitor element is formed in an element isolation region formed over a semiconductor substrate. The capacitor element includes a lower electrode and an upper electrode formed over the lower electrode through a capacitor insulating film. Basically, the lower electrode and the upper electrode are formed from polysilicon films and a cobalt silicide film formed over the surfaces of the polysilicon films. End portions of the cobalt silicide film formed over the upper electrode are spaced apart a distance from end portions of the upper electrode. Besides, end portions of the cobalt silicide film formed over the lower electrode are spaced apart a distance from boundaries between the upper electrode and the lower electrode.
    Type: Application
    Filed: August 16, 2012
    Publication date: December 6, 2012
    Inventors: Yoshiyuki Kawashima, Koichi Toba, Yasushi Ishii, Toshikazu Matsui, Takashi Hashimoto
  • Publication number: 20120299084
    Abstract: To improve the electric performance and reliability of a semiconductor device. A memory gate electrode of a split gate type nonvolatile memory is a metal gate electrode formed from a stacked film of a metal film 6a and a silicon film 6b over the metal film 6a. In an upper end part of the metal film 6a, a metal oxide portion 17 is formed by oxidation of a part of the metal film 6a. A control gate electrode of the split gate type nonvolatile memory is a metal gate electrode formed from a stacked film of a metal film 4a and the silicon film 4b over the metal film 4a.
    Type: Application
    Filed: May 21, 2012
    Publication date: November 29, 2012
    Inventors: Kentaro SAITO, Kazumasa YANAGISAWA, Yasushi ISHII, Koichi TOBA
  • Patent number: 8278169
    Abstract: The present invention provides a technology capable of reducing an area occupied by a nonvolatile memory while improving the reliability of the nonvolatile memory. In a semiconductor device, the structure of a code flash memory cell is differentiated from that of a data flash memory cell. More specifically, in the code flash memory cell, a memory gate electrode is formed only over the side surface on one side of a control gate electrode to improve a reading speed. In the data flash memory cell, on the other hand, a memory gate electrode is formed over the side surfaces on both sides of a control gate electrode. By using a multivalued memory cell instead of a binary memory cell, the resulting data flash memory cell can have improved reliability while preventing deterioration of retention properties and reduce its area.
    Type: Grant
    Filed: September 17, 2010
    Date of Patent: October 2, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Koichi Toba, Yasushi Ishii, Yoshiyuki Kawashima, Takashi Hashimoto, Kosuke Okuyama
  • Patent number: 8269266
    Abstract: Provided is a semiconductor device having, over a semiconductor substrate, a control gate electrode and a memory gate electrode which are adjacent to each other and constitute a nonvolatile memory. The height of the memory gate electrode is lower than the height of the control gate electrode. A metal silicide film is formed over the upper surface of the control gate electrode, but not formed over the upper surface of the memory gate electrode. The memory gate electrode has, over the upper surface thereof, a sidewall insulating film made of silicon oxide. This sidewall insulating film is formed in the same step as that for the formation of respective sidewall insulating films over the sidewalls of the memory gate electrode and the control gate electrode. The present invention makes it possible to improve the production yield and performance of the semiconductor device having a nonvolatile memory.
    Type: Grant
    Filed: June 28, 2010
    Date of Patent: September 18, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Koichi Toba, Yasushi Ishii, Yoshiyuki Kawashima, Satoru Machida, Munekatsu Nakagawa, Takashi Hashimoto
  • Patent number: 8258561
    Abstract: In connection with a semiconductor device including a capacitor element there is provided a technique capable of improving the reliability of the capacitor element. A capacitor element is formed in an element isolation region formed over a semiconductor substrate. The capacitor element includes a lower electrode and an upper electrode formed over the lower electrode through a capacitor insulating film. Basically, the lower electrode and the upper electrode are formed from polysilicon films and a cobalt silicide film formed over the surfaces of the polysilicon films. End portions of the cobalt silicide film formed over the upper electrode are spaced apart a distance from end portions of the upper electrode. Besides, end portions of the cobalt silicide film formed over the lower electrode are spaced apart a distance from boundaries between the upper electrode and the lower electrode.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: September 4, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshiyuki Kawashima, Koichi Toba, Yasushi Ishii, Toshikazu Matsui, Takashi Hashimoto
  • Publication number: 20120132978
    Abstract: A semiconductor device with a nonvolatile memory is provided which has improved characteristics. The semiconductor device includes a control gate electrode, a memory gate electrode disposed adjacent to the control gate electrode, a first insulating film, and a second insulating film including therein a charge storing portion. Among these components, the memory gate electrode is formed of a silicon film including a first silicon region positioned over the second insulating film, and a second silicon region positioned above the first silicon region. The second silicon region contains p-type impurities, and the concentration of p-type impurities of the first silicon region is lower than that of the p-type impurities of the second silicon region.
    Type: Application
    Filed: November 22, 2011
    Publication date: May 31, 2012
    Inventors: Koichi TOBA, Yasushi Ishi, Hiraku Chakihara, Kota Funayama, Yoshiyuki Kawashima, Takashi Hashimoto
  • Publication number: 20120068307
    Abstract: In connection with a semiconductor device including a capacitor element there is provided a technique capable of improving the reliability of the capacitor element. A capacitor element is formed in an element isolation region formed over a semiconductor substrate. The capacitor element includes a lower electrode and an upper electrode formed over the lower electrode through a capacitor insulating film. Basically, the lower electrode and the upper electrode are formed from polysilicon films and a cobalt silicide film formed over the surfaces of the polysilicon films. End portions of the cobalt silicide film formed over the upper electrode are spaced apart a distance from end portions of the upper electrode. Besides, end portions of the cobalt silicide film formed over the lower electrode are spaced apart a distance from boundaries between the upper electrode and the lower electrode.
    Type: Application
    Filed: November 30, 2011
    Publication date: March 22, 2012
    Inventors: Yoshiyuki Kawashima, Koichi Toba, Yasushi Ishii, Toshikazu Matsui, Takashi Hashimoto
  • Publication number: 20120068243
    Abstract: An improvement is achieved in the performance of semiconductor device including a nonvolatile memory. In a split-gate nonvolatile memory, between a memory gate electrode and a p-type well and between a control gate electrode and the memory gate electrode, an insulating film is formed. Of the insulating film, the portion between the lower surface of the memory gate electrode and the upper surface of a semiconductor substrate has silicon oxide films, and a silicon nitride film interposed between the silicon oxide films. Of the insulating film, the portion between a side surface of the control gate electrode and a side surface of the memory gate electrode is formed of a silicon oxide film, and does not have the silicon nitride film.
    Type: Application
    Filed: September 16, 2011
    Publication date: March 22, 2012
    Inventors: Yoshiyuki Kawashima, Koichi Toba
  • Patent number: 8084800
    Abstract: In connection with a semiconductor device including a capacitor element there is provided a technique capable of improving the reliability of the capacitor element. A capacitor element is formed in an element isolation region formed over a semiconductor substrate. The capacitor element includes a lower electrode and an upper electrode formed over the lower electrode through a capacitor insulating film. Basically, the lower electrode and the upper electrode are formed from polysilicon films and a cobalt silicide film formed over the surfaces of the polysilicon films. End portions of the cobalt silicide film formed over the upper electrode are spaced apart a distance from end portions of the upper electrode. Besides, end portions of the cobalt silicide film formed over the lower electrode are spaced apart a distance from boundaries between the upper electrode and the lower electrode.
    Type: Grant
    Filed: September 28, 2008
    Date of Patent: December 27, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshiyuki Kawashima, Koichi Toba, Yasushi Ishii, Toshikazu Matsui, Takashi Hashimoto
  • Patent number: 8070272
    Abstract: An ink cartridge 500 according to the invention is mounted on a carriage to reciprocate together with a coating head and serves to supply an ink in an air side containing portion 270 and a supply side containing portion 290 to the coating head. The air side containing portion 270 and first and second ink containing portions 292 and 294 are formed by a liquid containing concave portion 122 of a cartridge body 120 having one open surface opposed to a direction of a reciprocation of the coating head and a film 140 for sealing the open surface of the liquid containing concave portion 122. A stirring and moving member 711 is accommodated in the air side containing portion 270 and the second ink containing portion 294 in a movable state, respectively.
    Type: Grant
    Filed: June 16, 2005
    Date of Patent: December 6, 2011
    Assignee: Seiko Epson Corporation
    Inventor: Koichi Toba
  • Patent number: 8063433
    Abstract: A memory cell includes an ONO film composed of a stacked film of a silicon nitride film SIN which is a charge trapping portion and oxide films BOTOX and TOPOX positioned under and over the silicon nitride film, a memory gate electrode MG over the ONO film, a source region MS, and a drain region MD, and program or erase is performed by hot carrier injection in the memory cell. In the memory cell, a total concentration of N—H bonds and Si—H bonds contained in the silicon nitride film SIN is made to be 5×1020 cm?3 or less.
    Type: Grant
    Filed: April 24, 2008
    Date of Patent: November 22, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Tetsuya Ishimaru, Yasuhiro Shimamoto, Toshiyuki Mine, Yasunobu Aoki, Koichi Toba, Kan Yasui
  • Patent number: 7992984
    Abstract: A liquid container for supplying a liquid to a liquid consuming apparatus includes: a liquid containing section that contains the liquid; a liquid supply section that supplies the liquid to the liquid consuming apparatus; a liquid flow section that connects from the liquid containing section to the liquid supply section; a sensor that is provided in the liquid flow section and used for detecting presence or absence of the liquid at a corresponding position thereof; and a stirring member that stirs the liquid, the stirring member is provided at a position between the sensor and the liquid supply section in the liquid flow section.
    Type: Grant
    Filed: July 30, 2008
    Date of Patent: August 9, 2011
    Assignee: Seiko Epson Corporation
    Inventors: Koichi Toba, Shuichi Koganehira, Shohei Shiono
  • Publication number: 20110008943
    Abstract: The present invention provides a technology capable of reducing an area occupied by a nonvolatile memory while improving the reliability of the nonvolatile memory. In a semiconductor device, the structure of a code flash memory cell is differentiated from that of a data flash memory cell. More specifically, in the code flash memory cell, a memory gate electrode is formed only over the side surface on one side of a control gate electrode to improve a reading speed. In the data flash memory cell, on the other hand, a memory gate electrode is formed over the side surfaces on both sides of a control gate electrode. By using a multivalued memory cell instead of a binary memory cell, the resulting data flash memory cell can have improved reliability while preventing deterioration of retention properties and reduce its area.
    Type: Application
    Filed: September 17, 2010
    Publication date: January 13, 2011
    Inventors: Koichi TOBA, Yasushi Ishii, Yoshiyuki Kawashima, Takashi Hashimoto, Kosuke Okuyama