Patents by Inventor Koichi Yamada

Koichi Yamada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12153365
    Abstract: Provided is an image heating apparatus comprising: a first rotating member; a second rotating member that forms a nip with the first rotating member so as to nip the recording material therebetween; a heater that heats the nip; a conductive sheet member that is disposed so as to overlap with a part of the heater; and a restricting member that restricts relative positions between the sheet member and the heater. The restricting member is configured so as to restrict a relative movement between the sheet member and the heater in a first direction, which is a direction where the sheet member overlaps with a part of the heater, and to allow the relative movement in a second direction which is perpendicular to the first direction. A reinforcing land, that joins the heater and the sheet member, is disposed in a position that is electrically isolated.
    Type: Grant
    Filed: October 3, 2022
    Date of Patent: November 26, 2024
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Koichi Sekimizu, Koichi Yamada, Seiji Obata, Teruhiko Namiki
  • Patent number: 12135981
    Abstract: Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.
    Type: Grant
    Filed: June 9, 2023
    Date of Patent: November 5, 2024
    Assignee: Intel Corporation
    Inventors: Rajesh M. Sankaran, Gilbert Neiger, Narayan Ranganathan, Stephen R. Van Doren, Joseph Nuzman, Niall D. McDonnell, Michael A. O'Hanlon, Lokpraveen B. Mosur, Tracy Garrett Drysdale, Eriko Nurvitadhi, Asit K. Mishra, Ganesh Venkatesh, Deborah T. Marr, Nicholas P. Carter, Jonathan D. Pearce, Edward T. Grochowski, Richard J. Greco, Robert Valentine, Jesus Corbal, Thomas D. Fletcher, Dennis R. Bradford, Dwight P. Manley, Mark J. Charney, Jeffrey J. Cook, Paul Caprioli, Koichi Yamada, Kent D. Glossop, David B. Sheffield
  • Publication number: 20240321487
    Abstract: An electronic component that includes: a base body; a glass film covering at least a part of an outer surface of the base body; and an underlayer electrode covering a part of a surface of the glass film, wherein the base body contains a Mn oxide, the underlayer electrode contains a conductive metal and a glass component, the base body has a reaction layer containing a composite oxide of Mn and the conductive metal at an end portion of the underlayer electrode, and the reaction layer has a void.
    Type: Application
    Filed: May 22, 2024
    Publication date: September 26, 2024
    Inventors: Tomoya OOSHIMA, Yuuta HOSHINO, Mitsuru NAKANO, Koichi YAMADA, Miki SASAKI
  • Publication number: 20240304363
    Abstract: An electronic component that includes: a base body; a glass film covering an outer surface of the base body; and an external electrode on an outer surface of the glass film and having at least an underlayer electrode, wherein the glass film includes: a base portion containing silicon oxide and an oxide of one or more metal elements of an alkali metal and an alkaline earth metal; and a specific portion containing silicon oxide and an oxide of a same metal element as that of the base portion, and wherein a content ratio of the same metal element in the specific portion is smaller than a content ratio of the one or more metal elements in the base portion.
    Type: Application
    Filed: May 17, 2024
    Publication date: September 12, 2024
    Inventors: Tomoya OOSHIMA, Yuuta HOSHINO, Koichi YAMADA, Kojiro TOKIEDA, Miki SASAKI
  • Publication number: 20240136093
    Abstract: An electronic component that includes: a base body; wiring inside the base body; a glass film covering an outer surface of the base body; an underlying electrode electrically connected to the wiring and covering a part of the glass film; and a metal layer covering the underlying electrode, wherein the glass film includes an uncovered portion that is not covered with the underlying electrode and separated from an outer edge of the underlying electrode by more than 10 ?m, and a boundary portion that is not covered with the underlying electrode and not separated from the outer edge of the underlying electrode by more than 10 ?m, and a thickness of the boundary portion is larger than a thickness of the uncovered portion.
    Type: Application
    Filed: December 29, 2023
    Publication date: April 25, 2024
    Inventors: Tomoya OOSHIMA, Yuuta HOSHINO, Koichi YAMADA, Miki SASAKI, Mitsuru NAKANO
  • Publication number: 20240112835
    Abstract: An electronic component that includes: a base body having an outer surface defining a recess with an inner surface, wherein, when the recess is viewed in a direction orthogonal to the outer surface, at least a part of an outer edge of the recess is curved, and when the recess is viewed in a section orthogonal to the outer surface, at least a part of the inner surface of the recess is curved; a wiring inside the base body; and a glass film covering the outer surface of the base body and not covering the inner surface of the recess.
    Type: Application
    Filed: December 12, 2023
    Publication date: April 4, 2024
    Inventors: Tomoya OOSHIMA, Yuuta HOSHINO, Koichi YAMADA, Miki SASAKI
  • Publication number: 20240096524
    Abstract: An electronic component includes a ceramic body, and an external electrode on the ceramic body, the external electrode includes a base layer continuously covering an end surface of the ceramic body and a portion of a side surface bordering the end surface, and a plating layer covering the base layer, the ceramic body includes a recess open on the side surface, an opening of the recess includes a pair of edges, one edge of the opening is located within a covered region on the side surface covered with the base layer, and the other edge of the opening is spaced away from the covered region.
    Type: Application
    Filed: November 30, 2023
    Publication date: March 21, 2024
    Inventors: Kojiro TOKIEDA, Hideyuki SUZUKI, Koichi YAMADA, Miki SASAKI
  • Publication number: 20240040695
    Abstract: An electronic component that includes: an element body; and an insulating film covering an outer surface of the element body. The insulating film has a mix layer and a glass layer. The mix layer has a first glass and powder particles. The glass layer contains a second glass and has a smaller content percentage of the powder particles than the mix layer. The mix layer is on a side of the insulating film closer to the element body when viewed from the glass layer.
    Type: Application
    Filed: October 13, 2023
    Publication date: February 1, 2024
    Inventors: Tomoya OOSHIMA, Yuuta HOSHINO, Koichi YAMADA, Miki SASAKI, Hironobu KUBOTA
  • Publication number: 20240021346
    Abstract: An electronic component that includes: an element body; and an insulating film covering an outer surface of the element body. The element body has a crack that opens to the outer surface. In a cross section orthogonal to the outer surface, the crack has a first portion that extends from the opening and intersects an axis orthogonal to the outer surface. In addition, one portion of the insulating film penetrates into at least an inner space of the first portion of the crack.
    Type: Application
    Filed: September 27, 2023
    Publication date: January 18, 2024
    Inventors: Tomoya OOSHIMA, Yuuta HOSHINO, Koichi YAMADA, Miki SASAKI, Hironobu KUBOTA
  • Publication number: 20240021347
    Abstract: An electronic component that includes: a base body; and an insulating film covering an outer surface of the base body. The insulating film includes the film main body and a plurality of the thick film portions. A material of the film main body includes a glass. A material of the thick film portion is the same as the glass of the film main body. A thickness of the thick film portion is larger than an average thickness of the film main body.
    Type: Application
    Filed: September 27, 2023
    Publication date: January 18, 2024
    Inventors: Tomoya OOSHIMA, Yuuta HOSHINO, Koichi YAMADA, Miki SASAKI
  • Publication number: 20230418655
    Abstract: Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.
    Type: Application
    Filed: June 9, 2023
    Publication date: December 28, 2023
    Inventors: Rajesh M. SANKARAN, Gilbert NEIGER, Narayan RANGANATHAN, Stephen R. VAN DOREN, Joseph NUZMAN, Niall D. MCDONNELL, Michael A. O'HANLON, Lokpraveen B. MOSUR, Tracy Garrett DRYSDALE, Eriko NURVITADHI, Asit K. MISHRA, Ganesh VENKATESH, Deborah T. MARR, Nicholas P. CARTER, Jonathan D. PEARCE, Edward T. GROCHOWSKI, Richard J. GRECO, Robert VALENTINE, Jesus CORBAL, Thomas D. FLETCHER, Dennis R. BRADFORD, Dwight P. MANLEY, Mark J. CHARNEY, Jeffrey J. COOK, Paul CAPRIOLI, Koichi YAMADA, Kent D. GLOSSOP, David B. SHEFFIELD
  • Patent number: 11747756
    Abstract: At least an electrode of a first electrode group and at least an electrode of a second electrode group are formed in a region nearer to one edge portion of a substrate than to a center of the substrate in a longer-side direction of the substrate, and the electrode that is nearest to the second electrode group in the longer-side direction among the first electrode group formed in the region nearer to the one edge portion and the second electrode group are provided with a space between the electrode and the second electrode group.
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: September 5, 2023
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kazushi Nishikata, Ryota Ogura, Takafumi Suzuki, Seiji Obata, Koichi Yamada
  • Patent number: 11693691
    Abstract: Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.
    Type: Grant
    Filed: July 21, 2021
    Date of Patent: July 4, 2023
    Assignee: Intel Corporation
    Inventors: Rajesh M. Sankaran, Gilbert Neiger, Narayan Ranganathan, Stephen R. Van Doren, Joseph Nuzman, Niall D. McDonnell, Michael A. O'Hanlon, Lokpraveen B. Mosur, Tracy Garrett Drysdale, Eriko Nurvitadhi, Asit K. Mishra, Ganesh Venkatesh, Deborah T. Marr, Nicholas P. Carter, Jonathan D. Pearce, Edward T. Grochowski, Richard J. Greco, Robert Valentine, Jesus Corbal, Thomas D. Fletcher, Dennis R. Bradford, Dwight P. Manley, Mark J. Charney, Jeffrey J. Cook, Paul Caprioli, Koichi Yamada, Kent D. Glossop, David B. Sheffield
  • Publication number: 20230027168
    Abstract: Provided is an image heating apparatus comprising: a first rotating member; a second rotating member that forms a nip with the first rotating member so as to nip the recording material therebetween; a heater that heats the nip; a conductive sheet member that is disposed so as to overlap with a part of the heater; and a restricting member that restricts relative positions between the sheet member and the heater. The restricting member is configured so as to restrict a relative movement between the sheet member and the heater in a first direction, which is a direction where the sheet member overlaps with a part of the heater, and to allow the relative movement in a second direction which is perpendicular to the first direction. A reinforcing land, that joins the heater and the sheet member, is disposed in a position that is electrically isolated.
    Type: Application
    Filed: October 3, 2022
    Publication date: January 26, 2023
    Inventors: Koichi Sekimizu, Koichi Yamada, Seiji Obata, Teruhiko Namiki
  • Patent number: 11507412
    Abstract: A disclosed example apparatus includes memory; and processor circuitry to: identify a lock-protected section of instructions in the memory; replace lock/unlock instructions with transactional lock acquire and transactional lock release instructions to form a transactional process; and execute the transactional process in a speculative execution.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: November 22, 2022
    Assignee: Intel Corporation
    Inventors: Keqiang Wu, Jiwei Lu, Koichi Yamada, Yong-Fong Lee
  • Patent number: 11487230
    Abstract: Provided is an image heating apparatus comprising: a first rotating member; a second rotating member that forms a nip with the first rotating member so as to nip the recording material therebetween; a heater that heats the nip; a conductive sheet member that is disposed so as to overlap with a part of the heater; and a restricting member that restricts relative positions between the sheet member and the heater. The restricting member is configured so as to restrict a relative movement between the sheet member and the heater in a first direction, which is a direction where the sheet member overlaps with a part of the heater, and to allow the relative movement in a second direction which is perpendicular to the first direction. A reinforcing land, that joins the heater and the sheet member, is disposed in a position that is electrically isolated.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: November 1, 2022
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Koichi Sekimizu, Koichi Yamada, Seiji Obata, Teruhiko Namiki
  • Patent number: 11416281
    Abstract: Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.
    Type: Grant
    Filed: December 31, 2016
    Date of Patent: August 16, 2022
    Assignee: Intel Corporation
    Inventors: Rajesh M. Sankaran, Gilbert Neiger, Narayan Ranganathan, Stephen R. Van Doren, Joseph Nuzman, Niall D. McDonnell, Michael A. O'Hanlon, Lokpraveen B. Mosur, Tracy Garrett Drysdale, Eriko Nurvitadhi, Asit K. Mishra, Ganesh Venkatesh, Deborah T. Marr, Nicholas P. Carter, Jonathan D. Pearce, Edward T. Grochowski, Richard J. Greco, Robert Valentine, Jesus Corbal, Thomas D. Fletcher, Dennis R. Bradford, Dwight P. Manley, Mark J. Charney, Jeffrey J. Cook, Paul Caprioli, Koichi Yamada, Kent D. Glossop, David B. Sheffield
  • Patent number: 11373036
    Abstract: A control device (10) includes a spreadsheet process additional starting-up unit (162) and a spreadsheet process holding unit (163) configured to newly start up the spreadsheet software when the spreadsheet software has not been started up, and when the spreadsheet software has been started up configured to start up second spreadsheet software when spreadsheet software having been started up has been held such that the spreadsheet software is not terminated, a data entry unit (168) configured to enter information acquired by accessing to an information acquisition source in an information entry portion of a calculation sheet of the spreadsheet software, the calculation sheet being a calculation sheet in which a business logic is set for inter-cell computation on the calculation sheet, and a result acquisition unit (169) configured to acquire a determination result on the calculation sheet when a determination result for the information entered in the information entry portion is shown by the business logic re
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: June 28, 2022
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Nagatoshi Nawa, Akira Inoue, Koichi Yamada, Ikuko Takagi
  • Patent number: 11347853
    Abstract: A combination of hardware monitoring and binary translation software allow detection of return-oriented programming (ROP) exploits with low overhead and low false positive rates. Embodiments may use various forms of hardware to detect ROP exploits and indicate the presence of an anomaly to a device driver, which may collect data and pass the indication of the anomaly to the binary translation software to instrument the application code and determine whether an ROP exploit has been detected. Upon detection of the ROP exploit, the binary translation software may indicate the ROP exploit to an anti-malware software, which may take further remedial action as desired.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: May 31, 2022
    Assignee: MCAFEE, LLC
    Inventors: Palanivelrajan Rajan Shanmugavelayutham, Koichi Yamada, Vadim Sukhomlinov, Igor Muttik, Oleksandr Bazhaniuk, Yuriy Bulygin, Dmitri Dima Rubakha, Jennifer Eligius Mankin, Carl D. Woodward, Sevin F. Varoglu, Dima Mirkin, Alex Nayshtut
  • Publication number: 20220164218
    Abstract: Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.
    Type: Application
    Filed: July 21, 2021
    Publication date: May 26, 2022
    Inventors: Rajesh M. SANKARAN, Gilbert NEIGER, Narayan RANGANATHAN, Stephen R. VAN DOREN, Joseph NUZMAN, Niall D. MCDONNELL, Michael A. O'HANLON, Lokpraveen B. MOSUR, Tracy Garrett DRYSDALE, Eriko NURVITADHI, Asit K. MISHRA, Ganesh VENKATESH, Deborah T. MARR, Nicholas P. CARTER, Jonathan D. PEARCE, Edward T. GROCHOWSKI, Richard J. GRECO, Robert VALENTINE, Jesus CORBAL, Thomas D. FLETCHER, Dennis R. BRADFORD, Dwight P. MANLEY, Mark J. CHARNEY, Jeffrey J. COOK, Paul CAPRIOLI, Koichi YAMADA, Kent D. GLOSSOP, David B. SHEFFIELD