Patents by Inventor Koichi Yamada

Koichi Yamada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220148801
    Abstract: A rare earth sintered magnet is manufactured by preparing a R1-T-X sintered body having a major phase of R12T14X composition wherein R1 is a rare earth element(s) and essentially contains Pr and/or Nd, T is Fe, Co, Al, Ga, and/or Cu, and essentially contains Fe, and X is boron and/or carbon, forming an alloy powder containing 5?R2?60, 5?M?70, and 20<B?70, in at %, wherein R2 is a rare earth element(s) and essentially contains Dy and/or Tb, M is Fe, Cu, Al, Co, Mn, Ni, Sn, and/or Si, and B is boron, disposing the alloy powder on the sintered body, and heat treating the alloy-covered sintered body.
    Type: Application
    Filed: November 1, 2021
    Publication date: May 12, 2022
    Applicant: Shin-Etsu Chemical Co., Ltd.
    Inventors: Akira YAMADA, Tetsuya OHASHI, Koichi HIROTA
  • Publication number: 20220113952
    Abstract: A disclosed example includes generating a binary translation of a native code section in response to a determination that the binary translation of the native code section is not present in a translation cache; storing the binary translation of the native code section in the translation cache; determining that a stop has occurred during the generation of the binary translation; subsequent to the determination that the stop has occurred, generating a binary translation state map of at least a portion of the binary translation; storing, for at least a portion of a duration of the stop, the binary translation state map in memory; and discarding the binary translation state map from the memory upon termination of the stop, the binary translation state map to not exist after the discard of the binary translation state map.
    Type: Application
    Filed: December 23, 2021
    Publication date: April 14, 2022
    Inventors: Tugrul Ince, Koichi Yamada
  • Patent number: 11210074
    Abstract: The present disclosure is directed to a system for on-demand binary translation state map generation. Instead of interpreting the native code to be executed, binary translation circuitry (BT circuitry) may execute a binary translation (BT) in place of the native code. When a stop occurs (e.g., due to an interrupt, a modification of the native code, etc.), the BT circuitry may generate a binary translation state map (BT state map) that allows the location of the stop to be mapped back to the native code. Generation of the BT state map may involve determining a location and offset for the stop, performing region formation based on the location, loading instructions from the region (e.g., while accounting for the need to emulate instructions), forming the BT state map based at least on the size of the loaded instructions, and then mapping the stop back to the native code utilizing the offset.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: December 28, 2021
    Assignee: Intel Corporation
    Inventors: Tugrul Ince, Koichi Yamada
  • Publication number: 20210330197
    Abstract: In a biological information detection device, a frequency characteristic indicating a relation between a frequency and an intensity is acquired with respect to each of a plurality of biological signals input respectively from a plurality of biological activity sensors arranged at a plurality of positions different from each other to detect a biological activity of a person. A synthetic frequency characteristic indicating the relation between the frequency and the intensity is obtained by synthesizing a plurality of frequency characteristics acquired from the plurality of biological signals. Biological information on the biological activity is calculated based on the synthetic frequency characteristic.
    Type: Application
    Filed: July 6, 2021
    Publication date: October 28, 2021
    Inventors: Shunsuke SHIBATA, Takashi SAITOU, Koichi YAMADA
  • Patent number: 11126721
    Abstract: The disclosed embodiments generally relate to detecting malware through detection of micro-architectural changes (morphing events) when executing a code at a hardware level (e.g., CPU). An exemplary embodiment relates to a computer system having: a memory circuitry comprising an executable code; a central processing unit (CPU) in communication with the memory circuitry and configured to execute the code; a performance monitoring unit (PMU) associated with the CPU, the PMU configured to detect and count one or more morphing events associated with execution of the code and to determine if the counted number of morphine events exceed a threshold value; and a co-processor configured to initiate a memory scan of the memory circuitry to identify a malware in the code.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: September 21, 2021
    Assignee: INTEL CORPORATION
    Inventors: Alex Nayshtut, Vadim Sukhomlinov, Koichi Yamada, Ajay Harikumar, Venkat Gokulrangan
  • Patent number: 11093277
    Abstract: Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: August 17, 2021
    Assignee: Intel Corporation
    Inventors: Rajesh M. Sankaran, Gilbert Neiger, Narayan Ranganathan, Stephen R. Van Doren, Joseph Nuzman, Niall D. McDonnell, Michael A. O'Hanlon, Lokpraveen B. Mosur, Tracy Garrett Drysdale, Eriko Nurvitadhi, Asit K. Mishra, Ganesh Venkatesh, Deborah T. Marr, Nicholas P. Carter, Jonathan D. Pearce, Edward T. Grochowski, Richard J. Greco, Robert Valentine, Jesus Corbal, Thomas D. Fletcher, Dennis R. Bradford, Dwight P. Manley, Mark J. Charney, Jeffrey J. Cook, Paul Caprioli, Koichi Yamada, Kent D. Glossop, David B. Sheffield
  • Publication number: 20210223728
    Abstract: At least an electrode of a first electrode group and at least an electrode of a second electrode group are formed in a region nearer to one edge portion of a substrate than to a center of the substrate in a longer-side direction of the substrate, and the electrode that is nearest to the second electrode group in the longer-side direction among the first electrode group formed in the region nearer to the one edge portion and the second electrode group are provided with a space between the electrode and the second electrode group.
    Type: Application
    Filed: April 6, 2021
    Publication date: July 22, 2021
    Inventors: Kazushi Nishikata, Ryota Ogura, Takafumi Suzuki, Seiji Obata, Koichi Yamada
  • Patent number: 11048516
    Abstract: Systems, methods, and apparatuses for last branch record support are described. In an embodiment, a hardware processor core comprises a hardware execution unit to execute a branch instruction, at least two last branch record (LBR) registers to store a source and destination information of a branch taken during program execution, wherein an entry in a LBR register is to include an encoding of the branch, a write bit array to indicate which LBR register is architecturally correct, an architectural bit array to indicate when an LBR register has been written, and a plurality of top of stack pointers to indicate which LBR register in a LBR register stack is to be written.
    Type: Grant
    Filed: June 27, 2015
    Date of Patent: June 29, 2021
    Assignee: Intel Corporation
    Inventors: Paul Caprioli, Koichi Yamada, Jason M. Agron, Jiwei Lu
  • Publication number: 20210164848
    Abstract: A plurality of temperature sensors are disposed on a substrate and spaced from each other on a plurality of concentric virtual rings. The plurality of temperature sensors are each connected to one of a plurality of first common lines and one of a plurality of second common lines. The plurality of first common lines each include a first annular line portion located along the plurality of virtual rings, and a first connection line portion connecting the first annular line portion to at least one of the plurality of temperature sensors. The first annular line portion of each of the plurality of first common lines is located on an outer side of the plurality of virtual rings.
    Type: Application
    Filed: February 16, 2021
    Publication date: June 3, 2021
    Inventor: Koichi Yamada
  • Patent number: 10996598
    Abstract: At least an electrode of a first electrode group and at least an electrode of a second electrode group are formed in a region nearer to one edge portion of a substrate than to a center of the substrate in a longer-side direction of the substrate, and the electrode that is nearest to the second electrode group in the longer-side direction among the first electrode group formed in the region nearer to the one edge portion and the second electrode group are provided with a space between the electrode and the second electrode group.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: May 4, 2021
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kazushi Nishikata, Ryota Ogura, Takafumi Suzuki, Seiji Obata, Koichi Yamada
  • Patent number: 10984096
    Abstract: After a heuristic event counter in a processor has triggered a performance monitoring interrupt (PMI) when the processor was executing a target program in user mode, and after the processor has switched to kernel mode in response to the PMI, a heuristic event handler automatically performs preliminary analysis in kernel mode, without switching back to user mode, to determine whether heavyweight code analysis is warranted. The preliminary analysis comprises (a) obtaining an instruction pointer (IP) for the target program from a last branch record (LBR) buffer in the processor, (b) using transaction hardware in the processor to determine whether the IP from LBR buffer points to a readable page in memory, and (c) determining that heavyweight code analysis is not warranted in response to a determination that the page pointed to by the IP from LBR buffer is not readable. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: April 20, 2021
    Assignee: Intel Corporation
    Inventors: Koichi Yamada, Sevin F. Varoglu, Ajay Harikumar, Alex Nayshtut
  • Patent number: 10921744
    Abstract: An image heating apparatus including: a heater including heat generating elements, and electrodes electrically connected to the heat generating elements, respectively and arranged in an orthogonal direction of a conveyance direction of a recording material; and connectors for supplying electric power to electrodes, wherein the connectors include contact portions that come into contact with one of the electrodes, a first supporting portion that supports a first contact portion, and a second supporting portion that supports a second contact portion, the first supporting portion and the second supporting portion are arranged to be spaced apart from each other in the orthogonal direction, the first contact portion extends in a direction toward the second supporting portion, the second contact portion extends in a direction toward the first supporting portion, and the first contact portion and the second contact portion are in contact with the one of the electrodes at different positions.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: February 16, 2021
    Assignee: Canon Kabushiki Kaisha
    Inventor: Koichi Yamada
  • Publication number: 20210004531
    Abstract: A control device (10) includes a spreadsheet process additional starting-up unit (162) and a spreadsheet process holding unit (163) configured to newly start up the spreadsheet software when the spreadsheet software has not been started up, and when the spreadsheet software has been started up configured to start up second spreadsheet software when spreadsheet software having been started up has been held such that the spreadsheet software is not terminated, a data entry unit (168) configured to enter information acquired by accessing to an information acquisition source in an information entry portion of a calculation sheet of the spreadsheet software, the calculation sheet being a calculation sheet in which a business logic is set for inter-cell computation on the calculation sheet, and a result acquisition unit (169) configured to acquire a determination result on the calculation sheet when a determination result for the information entered in the information entry portion is shown by the business logic re
    Type: Application
    Filed: March 14, 2019
    Publication date: January 7, 2021
    Inventors: Nagatoshi NAWA, Akira Inoue, Koichi Yamada, Ikuko Takagi
  • Publication number: 20200401440
    Abstract: Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.
    Type: Application
    Filed: June 26, 2020
    Publication date: December 24, 2020
    Inventors: Rajesh M. SANKARAN, Gilbert NEIGER, Narayan RANGANATHAN, Stephen R. VAN DOREN, Joseph NUZMAN, Niall D. MCDONNELL, Michael A. O'HANLON, Lokpraveen B. MOSUR, Tracy Garrett DRYSDALE, Eriko NURVITADHI, Asit K. MISHRA, Ganesh VENKATESH, Deborah T. MARR, Nicholas P. CARTER, Jonathan D. PEARCE, Edward T. GROCHOWSKI, Richard J. GRECO, Robert VALENTINE, Jesus CORBAL, Thomas D. FLETCHER, Dennis R. BRADFORD, Dwight P. MANLEY, Mark J. CHARNEY, Jeffrey J. COOK, Paul CAPRIOLI, Koichi YAMADA, Kent D. GLOSSOP, David B. SHEFFIELD
  • Publication number: 20200401070
    Abstract: Provided is an image heating apparatus comprising: a first rotating member; a second rotating member that forms a nip with the first rotating member so as to nip the recording material therebetween; a heater that heats the nip; a conductive sheet member that is disposed so as to overlap with a part of the heater; and a restricting member that restricts relative positions between the sheet member and the heater. The restricting member is configured so as to restrict a relative movement between the sheet member and the heater in a first direction, which is a direction where the sheet member overlaps with a part of the heater, and to allow the relative movement in a second direction which is perpendicular to the first direction. A reinforcing land, that joins the heater and the sheet member, is disposed in a position that is electrically isolated.
    Type: Application
    Filed: June 16, 2020
    Publication date: December 24, 2020
    Inventors: Koichi Sekimizu, Koichi Yamada, Seiji Obata, Teruhiko Namiki
  • Patent number: 10839990
    Abstract: A chip resistor having a predetermined resistance value is manufactured by the following method. A resistive element is provided on an upper surface of an insulating substrate. The resistive element includes a wide portion, a first narrow portion extending from the wide portion, and a part extending from the wide portion, the first narrow portion has a smaller width than the wide portion. First and second electrodes are provided on the upper surface of the insulating substrate. The first electrode is located away from the wide portion. The first electrode contacts the first narrow portion. The first electrode overlaps the first narrow portion when viewed from above. The second electrode contacts the part of the resistive element. The second electrode overlaps the part of the resistive element when viewed from above. A distance between the narrow portion and the wide portion is determined so as to cause a resistance value between the first and second electrodes to be the predetermined resistance value.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: November 17, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Koichi Yamada, Shogo Nakayama
  • Patent number: 10803165
    Abstract: Particular embodiments described herein provide for an electronic device that can be configured to monitor code as it executes. The code can include self-modifying code. The system can log an event if the self-modifying code occurred in a GetPC address region.
    Type: Grant
    Filed: September 26, 2015
    Date of Patent: October 13, 2020
    Assignee: McAfee, LLC
    Inventors: Koichi Yamada, Palanivel Rajan Shanmugavelayutham, Greg W. Dalcher, Sravani Konda
  • Publication number: 20200319914
    Abstract: A disclosed example apparatus includes memory; and processor circuitry to: identify a lock-protected section of instructions in the memory; replace lock/unlock instructions with transactional lock acquire and transactional lock release instructions to form a transactional process; and execute the transactional process in a speculative execution.
    Type: Application
    Filed: April 28, 2020
    Publication date: October 8, 2020
    Inventors: Keqiang WU, Jiwei LU, Koichi YAMADA, Yong-Fong LEE
  • Patent number: 10789056
    Abstract: Technologies for binary translation include a computing device that allocates a translation cache shared by all threads associated with a corresponding execution domain. The computing device assigns a thread to an execution domain, translates original binary code of the thread to generate translated binary code, and installs the translated binary code into the corresponding translation cache for execution. The computing device may allocate a global region cache, generate region metadata associated with the original binary code of a thread, and store the region metadata in the global region cache. The original binary code may be translated using the region metadata. The computing device may allocate a global prototype cache, translate the original binary code of a thread to generate prototype code, and install the prototype code in the global prototype cache. The prototype code may be a non-executable version of the translated binary code. Other embodiments are described and claimed.
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: September 29, 2020
    Assignee: Intel Corporation
    Inventors: Koichi Yamada, Jose A. Baiocchi Paredes, Abhik Sarkar, Ajay Harikumar, Jiwei Lu
  • Patent number: 10725755
    Abstract: Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: July 28, 2020
    Assignee: Intel Corporation
    Inventors: David J. Sager, Ruchira Sasanka, Ron Gabor, Shlomo Raikin, Joseph Nuzman, Leeor Peled, Jason A. Domer, Ho-Seop Kim, Youfeng Wu, Koichi Yamada, Tin-Fook Ngai, Howard H. Chen, Jayaram Bobba, Jeffrey J. Cook, Omar M. Shaikh, Suresh Srinivas