Patents by Inventor Koichiro Yamashita

Koichiro Yamashita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160283822
    Abstract: A heating cooker includes a heating chamber that houses food, a heating unit that heats the food in the heating chamber, an imaging unit that acquires image data on the food after the food has been housed in the heating chamber, a setting unit that accepts a user input relating to heating control content defining a heating operation, a storage unit that stores control information in which the image data and the heating control content corresponding to the food specified from the image data are associated with each other, a heating start button that orders the start of the heating operation, and a storage update unit that associates the image data and the heating control content with each other and updates the control information within the storage unit, when the setting unit accepts the user input and then the heating start button orders the start of the heating operation.
    Type: Application
    Filed: October 22, 2014
    Publication date: September 29, 2016
    Inventors: Hirohisa IMAI, Hiroyoshi NOMURA, Koichiro YAMASHITA
  • Publication number: 20160277955
    Abstract: A communications network control method by a computer includes obtaining measurement area information indicating a measurement area of a sensor included in a communications node, the computer obtaining the measurement area information for each communications node in a communications node group that is included in a communications network and that is among plural communications nodes arranged in an arrangement area; obtaining divided area information indicating plural divided areas obtained by dividing the arrangement area; deriving for each divided area among the plural divided areas, a first value corresponding to a count of communications nodes that are in the communications node group and at least partially include the divided area in the measurement area indicated by the obtained measurement area information; and providing control of changing among the plural communications nodes, communications nodes included in the communications network, according to the first value derived for each divided area.
    Type: Application
    Filed: June 1, 2016
    Publication date: September 22, 2016
    Applicant: FUJITSU LIMITED
    Inventors: Takahisa Suzuki, Koichiro Yamashita, Toshiya Otomo, Hiromasa Yamauchi
  • Patent number: 9448931
    Abstract: An endian conversion method is executed by a CPU, and includes executing a program that includes endian conversion setting; and performing, when accessing an address of a main memory indicated in the endian conversion setting, endian conversion of data specified by the address of the main memory.
    Type: Grant
    Filed: September 17, 2013
    Date of Patent: September 20, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Akihito Kataoka, Koichiro Yamashita, Naoki Odate, Takahisa Suzuki, Hiromasa Yamauchi, Koji Kurihara, Toshiya Otomo
  • Patent number: 9442851
    Abstract: A multi-core processor system includes a memory unit that for each input destination thread defined as a thread to which given data is input, stores identification information of an assignment destination core for the input destination thread; and a multi-core processor that is configured to update, in the memory unit and when assignment of the input destination thread to a multi-core processor is detected, the identification information of the assignment destination core for the input destination thread; detect a writing request for the given data; identify based on the given data for which the writing request is detected, the updated identification information among information stored in the memory unit; and store the given data to a memory of the assignment destination core that is indicated in the updated identification information and among cores making up the multi-core processor.
    Type: Grant
    Filed: May 12, 2015
    Date of Patent: September 13, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Takahisa Suzuki, Koichiro Yamashita, Hiromasa Yamauchi, Koji Kurihara
  • Publication number: 20160255423
    Abstract: A system includes communications nodes, respectively having a sensor; and a communications apparatus that simultaneously requests the communications nodes to transmit sensor data. A first communications node among the communications nodes, when determining that among a first state where the communications apparatus includes the first communications node when requesting transmission and a second state where the communications apparatus excludes the first communications node when requesting transmission, the first communications node is in the second state: determines whether a predetermined difference is present between a predetermined value and the sensor data of the first communications node, and transmits a notification signal that notifies the communications apparatus of the predetermined difference, when determining that the predetermined difference is present.
    Type: Application
    Filed: May 12, 2016
    Publication date: September 1, 2016
    Applicant: FUJITSU LIMITED
    Inventors: Takahisa Suzuki, Toshiya Otomo, Hiromasa Yamauchi, Koichiro Yamashita
  • Publication number: 20160254945
    Abstract: A sensor node among sensor nodes that synchronously switch between a first state and a second state transmits an abnormality notification signal to a collecting apparatus when in the first state and an abnormality occurs at the sensor node. The sensor node, when in the second state, transmits to the communications apparatus, a data signal that differs from the abnormality notification signal. During each interval of the first state, the sensor node enters a third state during a first partial interval of the interval of the first state, and receives and transfers an abnormality notification signal transmitted by another sensor node among the sensor nodes. During each interval of the first state, the sensor node further enters a fourth state during a second partial interval of the interval of the first state and different from the first partial interval, and refrains from receiving the abnormality notification signal.
    Type: Application
    Filed: May 6, 2016
    Publication date: September 1, 2016
    Applicant: FUJITSU LIMITED
    Inventors: Toshiya Otomo, Koichiro Yamashita, Takahisa Suzuki, Hiromasa Yamauchi
  • Patent number: 9430388
    Abstract: A scheduler that causes a given core in a multi-core processor to determine if a priority level of a process that is to be executed by a core of the multi-core processor is greater than or equal to a threshold; save to a cache memory of each core that executes a process having a priority level greater than or equal to the threshold, data that is accessed by the process upon execution; save to a memory area different from the cache memory and to which access is relatively slower, data that is accessed by a process having a priority level not greater than or equal to the threshold; and save the data saved in the memory area, to a cache memory of a requesting core, when the requesting core issues an access request for the data saved in the memory area.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: August 30, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Hiromasa Yamauchi, Koichiro Yamashita, Takahisa Suzuki, Koji Kurihara
  • Patent number: 9430352
    Abstract: An information processing apparatus includes a processor configured to detect an unexecuted first thread and an unexecuted second thread; calculate standby power consumption of the first thread in a case of executing the second thread followed by the first thread, based on an execution period of the second thread and standby power consumption per unit time of the first thread; calculate standby power consumption of the second thread in a case of executing the first thread followed by the second thread, based on an execution period of the first thread and standby power consumption per unit time of the second thread; and determine an order of execution of the first thread and the second thread, based on comparison of the standby power consumption of first thread and the standby power consumption of the second thread.
    Type: Grant
    Filed: May 9, 2013
    Date of Patent: August 30, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Hiromasa Yamauchi, Koichiro Yamashita, Takahisa Suzuki, Koji Kurihara
  • Patent number: 9430015
    Abstract: A multiple-core processor system includes a memory unit storing the number of time intervals within a time bin, a time interval being a time interval between two consecutive operations; and a processor configured to: update the number of time intervals, specify a time stretch during which the number of time intervals stays above a threshold, and set, based on the number of time intervals, a power supply mode in which the multiple-core processor is supplied with power.
    Type: Grant
    Filed: October 18, 2012
    Date of Patent: August 30, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Takahisa Suzuki, Koichiro Yamashita, Hiromasa Yamauchi, Koji Kurihara
  • Patent number: 9430271
    Abstract: A data processing system includes an interrupt controller that counts, as an interrupt processing execution count, executions of interrupt processing by threads executed by data processing devices; and a processor that is configured to select one scheduling method from among a plurality of scheduling methods, based on the interrupt processing execution count.
    Type: Grant
    Filed: January 27, 2014
    Date of Patent: August 30, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Koji Kurihara, Koichiro Yamashita, Takahisa Suzuki, Hiromasa Yamauchi, Toshiya Otomo, Naoki Odate
  • Patent number: 9405470
    Abstract: A data processing system includes multiple data processing apparatuses; a peripheral apparatus; memory that is shared by the data processing apparatuses and the peripheral apparatus; peripheral memory provided corresponding to the peripheral apparatus; and a memory managing unit that secures in any one among the memory and the peripheral memory, an area for a thread that is based on thread information, the area being secured based on the thread information that is read out from a heap area that sequentially stores the thread information that is executed at any one among the data processing apparatuses and the peripheral apparatus.
    Type: Grant
    Filed: February 4, 2014
    Date of Patent: August 2, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Koichiro Yamashita, Hiromasa Yamauchi, Takahisa Suzuki, Koji Kurihara
  • Patent number: 9395803
    Abstract: A multi-core processor system includes a core configured to detect among multiple cores, a state of migration of first software from a first core to the core whose specific processing capacity value is lower than that of the first core; and set the processing capacity value of the first core at a time of the detection to be a processing capacity value that is lower than that before the migration when detecting the state of migration.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: July 19, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Hiromasa Yamauchi, Koichiro Yamashita, Takahisa Suzuki, Koji Kurihara
  • Patent number: 9390012
    Abstract: A multi-core processor system includes a processor configured to establish coherency of shared data values stored in a cache memory accessed by a multiple cores; detect a first thread executed by a first core among the cores; identify upon detecting the first thread, a second thread under execution by a second core other than the first core and among the cores; determine whether shared data commonly accessed by the first thread and the second thread is present; and stop establishment of coherency for a first cache memory corresponding to the first core and a second cache memory corresponding to the second core, upon determining that no shared data commonly accessed is present.
    Type: Grant
    Filed: February 24, 2015
    Date of Patent: July 12, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Takahisa Suzuki, Koichiro Yamashita, Hiromasa Yamauchi, Koji Kurihara
  • Patent number: 9384046
    Abstract: An information processing apparatus includes a computer configured to set respectively a storage location for each value of a common variable among threads of a thread group having write requests to write the values of the common variable of the threads in a given process, from a specific storage location defined in the write requests, to the storage locations respectively set for the threads; store, for each thread of the thread group, a value of the common variable to the storage location set for the thread; and read out in order of execution of the threads of the thread group defined in the given process and when all the threads in the thread group have ended, each value of the common variable stored at the first storing, and in the order of execution, overwrite a value in the specific storage location with each read value of the common variable.
    Type: Grant
    Filed: April 4, 2013
    Date of Patent: July 5, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Koji Kurihara, Koichiro Yamashita, Hiromasa Yamauchi, Takahisa Suzuki
  • Patent number: 9384797
    Abstract: A memory control method includes assigning based on a table to which an allocated device that executes a first process in a first application is registered, the first process in the first application to the allocated device registered; notifying a port connector of identification information of a port of memory, the port to be used by the first application, and registering a number of the port into the table; and allocating a storage area to the port and registering an address of the storage area into the table.
    Type: Grant
    Filed: July 24, 2013
    Date of Patent: July 5, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Hiromasa Yamauchi, Koichiro Yamashita, Takahisa Suzuki, Koji Kurihara, Toshiya Otomo
  • Patent number: 9384050
    Abstract: A scheduling method is executed by a first CPU and a second CPU. The scheduling method includes acquiring by the first CPU and when a first application is invoked, a first threshold for executing the first application; transmitting by the first CPU, a first threshold to the second CPU; and giving notification to the first CPU by the second CPU when an execution capability of the second CPU is greater than or equal to the first threshold, the notification indicating that the second CPU can execute the first application. The second CPU does not give notification to the first CPU when the execution capability of the second CPU is less than the first threshold.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: July 5, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Hiromasa Yamauchi, Koichiro Yamashita, Takahisa Suzuki, Koji Kurihara, Toshiya Otomo, Naoki Odate
  • Publication number: 20160179429
    Abstract: A multi-core processor system includes multiple cores and memory accessible from the cores, where a given core is configured to detect among the cores, first cores having a highest execution priority level; identify among the detected first cores, a second core that caused access conflict of the memory; and control a third core that is among the cores, excluding the first cores and the identified second core, the third core being controlled to execute for a given interval during an interval when the access conflict occurs, a thread that does not access the memory.
    Type: Application
    Filed: March 1, 2016
    Publication date: June 23, 2016
    Applicant: FUJITSU LIMITED
    Inventors: Koichiro YAMASHITA, Hiromasa Yamauchi, Kiyoshi Miyazaki
  • Publication number: 20160182359
    Abstract: A system has a group of nodes that perform multi-hop communication therebetween and a communications apparatus that communicates with a node included in the group of nodes. The node adds to data transmitted by the node, a hop count updated each time the data is transferred by the multi-hop communication and a reference hop count for the data to be transferred from the node to the communications apparatus, and transmits the data. The communications apparatus, when receiving the data, compares the reference hop count and the hop count added to the data, and based on a result of comparison, determines whether failure has occurred at a given node in the group of nodes.
    Type: Application
    Filed: March 1, 2016
    Publication date: June 23, 2016
    Applicant: FUJITSU LIMITED
    Inventors: Toshiya Otomo, Koichiro Yamashita, Takahisa Suzuki, Hiromasa Yamauchi
  • Patent number: 9367326
    Abstract: A multiprocessor system includes a master processor, at least one slave processor, and a synchronization unit. The master processor has a first flag indicating whether the master processor is in a task activation accepting state and a second flag reflective of a flag of a slave processor, iteratively updates the first flag at a frequency based on the volume of tasks processed by the master processor, and activates a task on the master processor or the slave processor based on the first flag and the second flag. Each slave processor has a third flag indicating whether the slave processor is in the task activation accepting state and iteratively updates the third flag at a frequency based on the volume of tasks processed by the slave processor. Tasks are allocated to the slave processor by the master processor. The synchronization unit synchronizes the third flag and the second flag.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: June 14, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Koji Kurihara, Koichiro Yamashita, Hiromasa Yamauchi, Takahisa Suzuki
  • Patent number: 9367311
    Abstract: A multi-core processor system includes a given core that includes a detecting unit that detects migration of a thread under execution by a synchronization source core to a synchronization destination core in the multi-core processor; an identifying unit that refers to a table identifying a combination of a thread and a register associated with the thread, and identifies a particular register corresponding to the thread for which migration was detected; a generating unit that generates synchronization control information identifying the synchronization destination core and the particular register; and a synchronization controller that, communicably connected to the multi-core processor, acquires from the given core, the synchronization control information, reads in from the particular register of the synchronization source core, a value of the particular register obtainable from the synchronization control information, and writes to the particular register of the synchronization destination core, the value.
    Type: Grant
    Filed: February 12, 2013
    Date of Patent: June 14, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Koichiro Yamashita, Hiromasa Yamauchi, Takahisa Suzuki, Koji Kurihara