Patents by Inventor Koji Dairiki

Koji Dairiki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8236629
    Abstract: Application form of and demand for an IC chip formed with a silicon wafer are expected to increase, and further reduction in cost is required. An object of the invention is to provide a structure of an IC chip and a process capable of producing at a lower cost. A feature of the invention is to use a metal film and a reactant having the metal film as a separation layer. An etching rate of the metal film or the reactant having metal is high, and a physical means in addition to a chemical means of etching the metal film or the reactant having metal can be used in the invention. Thus, the IDF chip can be manufactured more simply and easily in a short time.
    Type: Grant
    Filed: May 4, 2011
    Date of Patent: August 7, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshitaka Dozen, Tomoko Tamura, Takuya Tsurume, Koji Dairiki
  • Patent number: 8227851
    Abstract: It is an object of the invention to provide semiconductor devices which can protect privacy of consumers or holders of commercial products and control the communication range according to use, even when the semiconductor device which can exchange data without contact is mounted on the commercial products. A semiconductor device of the invention includes an element group including a plurality of transistors over a substrate; a first conductive film functioning as an antenna over the element group; a second conductive film surrounding the first conductive film; an insulating film covering the first and second end portions; and a third conductive film over the insulating film. The first conductive film is provided in the shape of a coil, and each end portion of the first conductive film is connected to the element group. First and second end portions of the second conductive film are not connected to each other.
    Type: Grant
    Filed: November 23, 2010
    Date of Patent: July 24, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tomoyuki Aoki, Koji Dairiki, Yuugo Goto
  • Publication number: 20120184064
    Abstract: A fragile layer is formed in a region at a depth of less than 1000 nm from one surface of a single crystal semiconductor substrate, and a first impurity semiconductor layer and a first electrode are formed at the one surface side. After bonding the first electrode and a supporting substrate, the single crystal semiconductor substrate is separated using the fragile layer or the vicinity as a separation plane, thereby forming a first single crystal semiconductor layer over the supporting substrate. An amorphous semiconductor layer is formed on the first single crystal semiconductor layer, and a second single crystal semiconductor layer is formed by heat treatment for solid phase growth of the amorphous semiconductor layer. A second impurity semiconductor layer having a conductivity type opposite to that of the first impurity semiconductor layer and a second electrode are formed over the second single crystal semiconductor layer.
    Type: Application
    Filed: March 22, 2012
    Publication date: July 19, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Fumito ISAKA, Sho KATO, Koji DAIRIKI
  • Patent number: 8207026
    Abstract: To provide a method for manufacturing a thin film transistor and a display device using a small number of masks, a thin film transistor is manufactured in such a manner that a first conductive film, an insulating film, a semiconductor film, an impurity semiconductor film, and a second conductive film are stacked; then, a resist mask is formed thereover; first etching is performed to form a thin-film stack body; second etching in which the first conductive film is side-etched is performed by dry-etching to form a gate electrode layer; and a source electrode, a drain electrode, and the like are formed. Before the dry etching, it is preferred that at least a side surface of the etched semiconductor film be oxidized.
    Type: Grant
    Filed: January 25, 2010
    Date of Patent: June 26, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideomi Suzawa, Takafumi Mizoguchi, Koji Dairiki, Mayumi Mikami, Yumiko Saito
  • Publication number: 20120146240
    Abstract: To provide a semiconductor device in which wireless communication is performed between devices formed over different substrates and connection defects of wirings are reduced. A first device having a first antenna is provided over a first substrate, a second device having a second antenna which can communicate with the first antenna is provided over a second substrate, and the first substrate and the second substrate are bonded to each other to manufacture a semiconductor device. The first substrate and the second substrate are bonded to each other by bonding with a bonding layer interposed therebetween, anodic bonding, or surface activated bonding.
    Type: Application
    Filed: March 24, 2008
    Publication date: June 14, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Koji DAIRIKI, Konami IZUMI
  • Publication number: 20120146026
    Abstract: A photoelectric conversion, element including a first gate electrode, a first gate insulating layer, a crystalline semiconductor layer an amorphous semiconductor layer, an impurity semiconductor layer, a source electrode and a drain electrode in contact with the impurity semiconductor layer, a second gate insulating layer covering; a region between the source electrode and the drain electrode, and a second gate electrode over the second gate insulating layer. In the photoelectric conversion element, a Sight-receiving portion is provided in the region between the source electrode and the drain electrode, the first gate electrode includes a light-shielding material and overlaps with the entire surface of the crystalline semiconductor layer and the amorphous semiconductor layer, the second gate electrode includes a light-transmitting material and overlaps with, the light-receiving portion, and the first gate electrode is electrically connected to the source electrode or the drain electrode is provided.
    Type: Application
    Filed: December 6, 2011
    Publication date: June 14, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Tsudoi Nagi, Koji Dairiki
  • Patent number: 8187956
    Abstract: A method for forming a microcrystalline semiconductor film over a base formed of a different material, which has high crystallinity in the entire film and at an interface with the base, is proposed. Further, a method for manufacturing a thin film transistor including a microcrystalline semiconductor film with high crystallinity is proposed. Furthermore, a method for manufacturing a photoelectric conversion device including a microcrystalline semiconductor film with high crystallinity is proposed. By forming crystal nuclei with high density and high crystallinity over a base film and then growing crystals in a semiconductor from the crystal nuclei, a microcrystalline semiconductor film which has high crystallinity at an interface with the base film, which has high crystallinity in crystal grains, and which has high adhesion between the adjacent crystal grains is formed.
    Type: Grant
    Filed: November 25, 2008
    Date of Patent: May 29, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yasuhiro Jinbo, Hidekazu Miyairi, Koji Dairiki
  • Publication number: 20120129288
    Abstract: A display device including a thin film transistor with high electric characteristics and high reliability, and a method for manufacturing the display device with high mass-productivity. In a display device including an inverted-staggered channel-stop-type thin film transistor, the inverted-staggered channel-stop-type thin film transistor includes a microcrystalline semiconductor film including a channel formation region, and an impurity region containing an impurity element of one conductivity type is selectively provided in a region which is not overlapped with source and drain electrodes, in the channel formation region of the microcrystalline semiconductor film.
    Type: Application
    Filed: January 31, 2012
    Publication date: May 24, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Satoshi KOBAYASHI, Ikuko Kawamata, Koji Dairiki, Shigeki Komori, Toshiyuki Isa, Shunpei Yamazaki
  • Patent number: 8168973
    Abstract: The thin film transistor includes, over a substrate having an insulating surface, a gate insulating layer covering a gate electrode, an amorphous semiconductor layer over the gate insulating layer, a semiconductor layer including an impurity element imparting one conductivity type over the amorphous semiconductor layer. The amorphous semiconductor layer comprises an NH radical. Defects of the amorphous semiconductor layer are reduced by cross-linking dangling bonds with the NH radical in the amorphous semiconductor layer.
    Type: Grant
    Filed: May 15, 2009
    Date of Patent: May 1, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Koji Dairiki, Hidekazu Miyairi, Akiharu Miyanaga, Takuya Hirohashi
  • Publication number: 20120097963
    Abstract: A first shape of semiconductor region having on its one side a plurality of sharp convex top-end portions is formed first and a continuous wave laser beam is used for radiation from the above region so as to crystallize the first shape of semiconductor region. A continuous wave laser beam condensed in one or plural lines is used for the laser beam. The first shape of semiconductor region is etched to form a second shape of semiconductor region in which a channel forming region and a source and drain region are formed. The second shape of semiconductor region is disposed so that a channel foaming range would be formed on respective crystal regions extending from the plurality of convex end portions. A semiconductor region adjacent to the channel forming region is eliminated.
    Type: Application
    Filed: December 30, 2011
    Publication date: April 26, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Chiho KOKUBO, Aiko Shiga, Shunpei Yamazaki, Hidekazu Miyairi, Koji Dairiki, Koichiro Tanaka
  • Patent number: 8143087
    Abstract: A fragile layer is formed in a region at a depth of less than 1000 nm from one surface of a single crystal semiconductor substrate, and a first impurity semiconductor layer and a first electrode are formed at the one surface side. After bonding the first electrode and a supporting substrate, the single crystal semiconductor substrate is separated using the fragile layer or the vicinity as a separation plane, thereby forming a first single crystal semiconductor layer over the supporting substrate. An amorphous semiconductor layer is formed on the first single crystal semiconductor layer, and a second single crystal semiconductor layer is formed by heat treatment for solid phase growth of the amorphous semiconductor layer. A second impurity semiconductor layer having a conductivity type opposite to that of the first impurity semiconductor layer and a second electrode are formed over the second single crystal semiconductor layer.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: March 27, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Fumito Isaka, Sho Kato, Koji Dairiki
  • Patent number: 8138614
    Abstract: It is an object to provide a semiconductor device capable of transmitting and receiving data with a reader/writer and reducing breakdown or interference due to static electricity. A semiconductor device includes a semiconductor integrated circuit, a conductive layer serving as an antenna that is connected to the semiconductor integrated circuit, and a substrate interposing the semiconductor integrated circuit and the conductive layer, where at least one of a layer forming the semiconductor integrated circuit, a layer covering the semiconductor integrated circuit, and the substrate is formed from a conductive polymer. In accordance with the above structure, wireless communication with a reader/writer is possible, and breakdown or malfunction in the semiconductor integrated circuit due to static electricity is reduced.
    Type: Grant
    Filed: February 5, 2007
    Date of Patent: March 20, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Koji Dairiki
  • Patent number: 8138032
    Abstract: A thin film transistor includes, over a substrate having an insulating surface, a gate insulating layer covering a gate electrode; a semiconductor layer which includes a plurality of crystalline regions in an amorphous structure and which forms a channel formation region, in contact with the gate insulating layer; a semiconductor layer including an impurity element imparting one conductivity type, which forms source and drain regions; and a buffer layer including an amorphous semiconductor between the semiconductor layer and the semiconductor layer including an impurity element imparting one conductivity type. The crystalline regions have an inverted conical or inverted pyramidal crystal particle which grows approximately radially in a direction in which the semiconductor layer is deposited, from a position away from an interface between the gate insulating layer and the semiconductor layer.
    Type: Grant
    Filed: April 14, 2009
    Date of Patent: March 20, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hidekazu Miyairi, Koji Dairiki, Yuji Egi, Yasuhiro Jinbo, Toshiyuki Isa
  • Publication number: 20120061676
    Abstract: A highly reliable transistor in which change in electrical characteristics is suppressed is provided. A highly reliable transistor in which change in electrical characteristics is suppressed is manufactured with high productivity. A display device with less image deterioration over time is provided. An inverted staggered thin film transistor which includes, between a gate insulating film and impurity semiconductor films functioning as source and drain regions, a semiconductor stacked body including a microcrystalline semiconductor region and a pair of amorphous semiconductor regions. In the microcrystalline semiconductor region, the nitrogen concentration on the gate insulating film side is low and the nitrogen concentration in a region in contact with the amorphous semiconductor is high. Further, an interface with the amorphous semiconductor has unevenness.
    Type: Application
    Filed: September 7, 2011
    Publication date: March 15, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Yuji EGI, Tetsuhiro TANAKA, Toshiyuki ISA, Hidekazu MIYAIRI, Koji DAIRIKI, Yoichi KUROSAWA, Kunihiko SUZUKI
  • Publication number: 20120064677
    Abstract: Provided is a method for manufacturing a semiconductor device with fewer masks and in a simple process. A gate electrode is formed. A gate insulating film, a semiconductor film, an impurity semiconductor film, and a conductive film are stacked in this order, covering the gate electrode. A source electrode and a drain electrode are formed by processing the conductive film. A source region, a drain region, and a semiconductor layer, an upper part of a portion of which does not overlap with the source region and the drain region is removed, are formed by processing the upper part of the semiconductor film, while the impurity semiconductor film is divided. A passivation film over the gate insulating film, the semiconductor layer, the source region, the drain region, the source electrode, and the drain electrode are formed. An etching mask is formed over the passivation film.
    Type: Application
    Filed: September 6, 2011
    Publication date: March 15, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Hidekazu MIYAIRI, Koji DAIRIKI, Shunpei YAMAZAKI, Ryo ARASAWA
  • Patent number: 8133771
    Abstract: A display device including a thin film transistor with high electric characteristics and high reliability, and a method for manufacturing the display device with high mass-productivity. In a display device including an inverted-staggered channel-stop-type thin film transistor, the inverted-staggered channel-stop-type thin film transistor includes a microcrystalline semiconductor film including a channel formation region, and an impurity region containing an impurity element of one conductivity type is selectively provided in a region which is not overlapped with source and drain electrodes, in the channel formation region of the microcrystalline semiconductor film.
    Type: Grant
    Filed: July 16, 2010
    Date of Patent: March 13, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoshi Kobayashi, Ikuko Kawamata, Koji Dairiki, Shigeki Komori, Toshiyuki Isa, Shunpei Yamazaki
  • Patent number: 8124972
    Abstract: The thin film transistor includes a gate insulating layer covering a gate electrode, over a substrate having an insulating surface; a semiconductor layer forming a channel formation region, in which a plurality of crystal regions is included in an amorphous structure; an impurity semiconductor layer imparting one conductivity type which forms a source region and a drain region; and a buffer layer formed from an amorphous semiconductor, which is located between the semiconductor layer and the impurity semiconductor layer. The thin film transistor includes the crystal region which includes minute crystal grains and inverted conical or inverted pyramidal grain each of which grows approximately radially from a position away from an interface between the gate insulating layer and the semiconductor layer toward a direction in which the semiconductor layer is deposited in a region which does not reach the impurity semiconductor layer.
    Type: Grant
    Filed: April 24, 2009
    Date of Patent: February 28, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Koji Dairiki, Hidekazu Miyairi, Toshiyuki Isa, Akiharu Miyanaga, Takuya Hirohashi, Shunpei Yamazaki, Takeyoshi Watabe
  • Patent number: 8119468
    Abstract: Disclosed is a thin film transistor which includes, over a substrate having an insulating surface, a gate insulating layer covering a gate electrode; a semiconductor layer which functions as a channel formation region; and a semiconductor layer including an impurity element imparting one conductivity type. The semiconductor layer exists in a state that a plurality of crystalline particles is dispersed in an amorphous silicon and that the crystalline particles have an inverted conical or inverted pyramidal shape. The crystalline particles grow approximately radially in a direction in which the semiconductor layer is deposited. Vertexes of the inverted conical or inverted pyramidal crystal particles are located apart from an interface between the gate insulating layer and the semiconductor layer.
    Type: Grant
    Filed: April 14, 2009
    Date of Patent: February 21, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hidekazu Miyairi, Koji Dairiki, Yuji Egi, Yasuhiro Jinbo, Toshiyuki Isa
  • Patent number: 8093593
    Abstract: A first shape of semiconductor region having on its one side a plurality of sharp convex top-end portions is formed first and a continuous wave laser beam is used for radiation from the above region so as to crystallize the first shape of semiconductor region. A continuous wave laser beam condensed in one or plural lines is used for the laser beam. The first shape of semiconductor region is etched to form a second shape of semiconductor region in which a channel forming region and a source and drain region are formed. The second shape of semiconductor region is disposed so that a channel forming range would be formed on respective crystal regions extending from the plurality of convex end portions. A semiconductor region adjacent to the channel forming region is eliminated.
    Type: Grant
    Filed: September 7, 2006
    Date of Patent: January 10, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Chiho Kokubo, Aiko Shiga, Shunpei Yamazaki, Hidekazu Miyairi, Koji Dairiki, Koichiro Tanaka
  • Publication number: 20110309361
    Abstract: A photoelectric conversion element includes a first conductive layer over a substrate; a first insulating layer covering the first conductive layer; a first semiconductor layer over the first insulating layer; a second conductive layer formed over the first semiconductor layer; an impurity semiconductor layer over the second semiconductor layer; a second conductive layer over the impurity semiconductor layer; a second insulating layer covering the first semiconductor layer and the second conductive layer; and a light-transmitting third conductive layer over the second insulating layer. A first opening and a second opening are formed in the second insulating layer. In the first opening, the first semiconductor layer is connected to the third conductive layer. In the second opening, the first conductive layer is connected to the third conductive layer. In the first opening, a light-receiving portion surrounded by an electrode formed of the second conductive layer is provided.
    Type: Application
    Filed: June 17, 2011
    Publication date: December 22, 2011
    Inventors: Koji Dairiki, Hidekazu Miyairi, Tsudoi Nagi