Patents by Inventor Koji Fukuda

Koji Fukuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11003810
    Abstract: A simulation system obtains multiple random number vectors and a parameter vector and calculates realized values of the behavior of a stochastic system corresponding to each obtained random number vector. Based on each obtained random number vector, on the obtained parameter vector, and on a weight function, the system calculates the weight of each obtained random number vector regarding each of the parameters in the obtained parameter vector, and calculates an evaluation value of the behavior of the stochastic system corresponding to each obtained random number vector. Based on the calculated behavior evaluation value corresponding to each obtained random number vector and on the weight of each obtained random number vector regarding the parameter selected from the obtained parameter vector, the system calculates the sensitivity of an expected value for the behavior evaluation value of the stochastic system with regard to the selected parameter.
    Type: Grant
    Filed: August 25, 2014
    Date of Patent: May 11, 2021
    Assignee: HITACHI, LTD.
    Inventors: Koji Fukuda, Yasuyuki Kudo
  • Publication number: 20180260744
    Abstract: There is provided a system that forecasts an index value of a predetermined day based on input data of the predetermined day in which result data of an index value of a day before the predetermined day is stored, similarity between the input data of the predetermined day and each of the stored result data is calculated, a weight is calculated for each result data based on the calculated similarity, and a forecasted index value of the predetermined day is prepared based on the calculated weight, the result data, and the input data of the predetermined day.
    Type: Application
    Filed: September 2, 2015
    Publication date: September 13, 2018
    Applicant: HITACHI, LTD.
    Inventors: Koji FUKUDA, Tadayuki MATSUMURA
  • Publication number: 20170235862
    Abstract: A simulation system obtains multiple random number vectors and a parameter vector and calculates realized values of the behavior of a stochastic system corresponding to each obtained random number vector. Based on each obtained random number vector, on the obtained parameter vector, and on a weight function, the system calculates the weight of each obtained random number vector regarding each of the parameters in the obtained parameter vector, and calculates an evaluation value of the behavior of the stochastic system corresponding to each obtained random number vector. Based on the calculated behavior evaluation value corresponding to each obtained random number vector and on the weight of each obtained random number vector regarding the parameter selected from the obtained parameter vector, the system calculates the sensitivity of an expected value for the behavior evaluation value of the stochastic system with regard to the selected parameter.
    Type: Application
    Filed: August 25, 2014
    Publication date: August 17, 2017
    Inventors: Koji FUKUDA, Yasuyuki KUDO
  • Publication number: 20150324482
    Abstract: A decision-making support system which is a client-server system comprising: multiple servers; a client having a display; a network; and a database. On the basis of data acquisition conditions supplied via the client the multiple servers acquire from the data base on multiple distributed processing platforms, a first data group spanning from the past to the present, and generate a first network graph for the time from the past to the present. The multiple servers also execute multiple simulations based on the first data group, on the basis of provided simulation conditions, and generate second and third network graphs for a time not included in the first data group or for the future. The client receives the results of the generation of these network graphs and displays on the display the first through third network graphs spanning from the past to the present, and to the future, thereby providing the user with a scenario map.
    Type: Application
    Filed: November 29, 2012
    Publication date: November 12, 2015
    Applicant: Hitachi, Ltd
    Inventors: TAKESHI KATO, Koji FUKUDA, Masaki HAMAMOTO, Yasuyuki KUDO, Hiroyuki MIZUNO
  • Patent number: 9035173
    Abstract: A back electrode type solar cell in which a no-electrode-formed region where no electrode is placed is provided in a part of a peripheral portion of a back surface of the back electrode type solar cell such that a line connecting end portions of a plurality of electrodes to one another includes a partially inwardly recessed region and the no-electrode-formed region is located adjacent to each of an electrode for n-type and an electrode for p-type adjacent to each other, a solar cell module, a method of manufacturing a back electrode type solar cell with interconnection sheet, and a method of manufacturing a solar cell module are provided.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: May 19, 2015
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Shinsuke Naito, Yasushi Sainoo, Tomohiro Nishina, Kohjiroh Morii, Tomoyo Shiraki, Akiko Tsunemi, Takayuki Yamada, Masatomo Tanahashi, Koji Fukuda
  • Patent number: 9020685
    Abstract: In the disclosed method of measuring contact failure and contact failure measuring device, the magnitude of the excessive response fluctuation of the inductive magnetic field around a harness under measurement when an external force is applied to a terminal fitting part of the harness is detected by a magnetic sensor, and the result is displayed as an index of the quality of the contact state of the terminal fitting part.
    Type: Grant
    Filed: February 22, 2011
    Date of Patent: April 28, 2015
    Assignee: Honda Motor Co., Ltd.
    Inventors: Susumu Maruyama, Hideyuki Tsuchikiri, Koji Fukuda, Atsushi Demachi
  • Patent number: 8772880
    Abstract: A high-speed semiconductor integrated circuit device is achieved by adjusting an offset voltage. For example, dummy NMOS transistors MND1 (MND1a and MND1b) and MND2 (MND2a and MND2b) are connected to drain outputs of NMOS transistors MN1 and MN2 operated according to differential input signals Din_p and Din_n, respectively. The MND1 is arranged adjacent to the MN1, and a source of the MND1a and a drain of the MN1 share a diffusion layer. The MND2 is arranged adjacent to the MN2, and a source of the MND2a and a drain of the MN2 share a diffusion layer. The MND1 and the MND2 function as dummy transistors for suppressing variations in process of the MN1 and the MN2 and, and besides, they also function as means for adjusting the offset voltage by appropriately applying an offset-amount setting signal OFST to each gate to provide a capacitor to either the MN1 or the MN2.
    Type: Grant
    Filed: October 4, 2010
    Date of Patent: July 8, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Koji Fukuda, Hiroki Yamashita
  • Publication number: 20140038758
    Abstract: A tensioner includes a movable member, a fixed member, biasing means provided between the fixed member and the movable member and configured to bias the movable member along a pressing direction, and a damping member provided between the fixed member and the movable member and configured to damp the pivoting movement of the movable member. The damping member is made of a resin composition whose sliding friction force damps the pivoting movement of the movable member, and a contact angle between the resin composition and water is 70° to 100°, both inclusive.
    Type: Application
    Filed: October 11, 2013
    Publication date: February 6, 2014
    Inventors: Saki JINDAI, Koji FUKUDA
  • Publication number: 20130298988
    Abstract: There is provided a solar battery, including: a solar cell including a porous electrode provided on at least one surface of a substrate; a conductive wire electrically connected to the porous electrode; and an adhesive material provided between the porous electrode and the conductive wire, wherein a part of the adhesive material penetrates into the porous electrode. There is also provided a method of manufacturing the solar battery.
    Type: Application
    Filed: December 14, 2011
    Publication date: November 14, 2013
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Koji Fukuda, Tomoo Imataki, Yasushi Sainoo, Tomohiro Nishina, Shinsuke Naito, Akiko Tsunemi, Tomoyo Shiraki, Takayuki Yamada, Masatomo Tanahashi
  • Publication number: 20130284260
    Abstract: A back electrode type solar cell in which a no-electrode-formed region where no electrode is placed is provided in a part of a peripheral portion of a back surface of the back electrode type solar cell such that a line connecting end portions of a plurality of electrodes to one another includes a partially inwardly recessed region and the no-electrode-formed region is located adjacent to each of an electrode for n-type and an electrode for p-type adjacent to each other, a solar cell module, a method of manufacturing a back electrode type solar cell with interconnection sheet, and a method of manufacturing a solar cell module are provided.
    Type: Application
    Filed: November 29, 2011
    Publication date: October 31, 2013
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Shinsuke Naito, Yasushi Sainoo, Tomohiro Nishina, Kohjiroh Morii, Tomoyo Shiraki, Akiko Tsunemi, Takayuki Yamada, Masatomo Tanahashi, Koji Fukuda
  • Patent number: 8503595
    Abstract: The invention relates to a clock generation circuit and a signal reproduction circuit including the clock generation circuit, and, more particularly, the invention provides a data judgment/phase comparison circuit capable of performing both of data judgment and phase comparison by a single-phase clock, and provides a CDR (Clock Data Recovery) circuit including the data judgment/phase comparison circuit. The same data and clock are inputted to two data judging units C_GOOD and C_BAD each having a different data determination period (setup/hold time) required for correctly judging a data, and an output of the data judging unit C_GOOD having a shorter required data determination period is taken as a data output of the data judgment/phase comparison circuit. When the outputs of both of the data judging units are different from each other, a signal Early indicating that a clock phase is too early or a signal Late indicating that the clock phase is too late is outputted.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: August 6, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Koji Fukuda, Hiroki Yamashita
  • Patent number: 8493103
    Abstract: Disclosed is an output driver circuit capable of realizing reduction in power consumption, and/or enhancement in transmission waveform quality in addition to an increase in transmission speed. The output driver circuit is provided with, for example, a voltage-signal generation circuit block VSG_BK for driving positive negative output-nodes (TXP, TXN) by voltage, -pulse-signal generation circuits PGEN1, PGEN 2 for generating a pulse signal upon a transition of data input signals DIN_P, DIN_N, and current-signal generation circuit blocks ISG_BKp1, ISG_BKn1, for driving TXP, TXN by current for the duration of a pulse width of the pulse-signal. The current-signal generation circuit block executes high-speed charging of parasitic capacitors Cp1, Cp2, occurring to TXP, TXN, respectively, while executing charging of parasitic capacitors Cp1, Cp2, occurring to impedance Z0 respectively.
    Type: Grant
    Filed: January 8, 2011
    Date of Patent: July 23, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Koji Fukuda, Hiroki Yamashita
  • Patent number: 8483579
    Abstract: A high-accuracy phase detector circuit compatible with a 1/N rate architecture is provided. The phase detector circuit has as many as N track-and-hold circuits for tracking and holding N-phase clock signals CLK—1 to CLK_N in synchronization with a rising edge of input data signal DIN. Out of the N-phase clock signals CLK—1 to CLK_N outputted from as many track-and-hold circuits, only the one whose rising edge is most synchronized with a rising edge of the input data signal DIN is selected and outputted as a phase difference signal.
    Type: Grant
    Filed: August 10, 2009
    Date of Patent: July 9, 2013
    Assignee: Hitachi, Ltd.
    Inventor: Koji Fukuda
  • Publication number: 20120319854
    Abstract: In the disclosed method of measuring contact failure and contact failure measuring device, the magnitude of the excessive response fluctuation of the inductive magnetic field around a harness under measurement when an external force is applied to a terminal fitting part of the harness is detected by a magnetic sensor, and the result is displayed as an index of the quality of the contact state of the terminal fitting part.
    Type: Application
    Filed: February 22, 2011
    Publication date: December 20, 2012
    Applicant: HONDA MOTOR CO., LTD.
    Inventors: Susumu Maruyama, Hideyuki Tsuchikiri, Koji Fukuda, Atsushi Demachi
  • Patent number: 8311157
    Abstract: A signal recovery circuit capable of expanding the receive margin is provided. The signal recovery circuit comprises for example a clock generator unit CLK_GEN for generating the clock signals CLKa, CLKb, and CLKc, a window width control unit WW_CTL, and a clock data discriminator unit CD_JGE for generating a phase detector signal (EARLY, LATE) when for example a data signal Di pulse edge enters between the CLKa and CLKb, or between the CLKb and CLKc, and the clock generator unit. Along with exerting control based on these phase detection signals to maintain the mutual phase differential of the overall phase of CLKa, CLKb, CLKc so as to prevent intrusion of the above described Di edge, the CLK_GEN also regulates the phase differential between CLKa and CLKb, and the phase differential between CLKb and CLKc based on a signal (Sww) from the WW_CTL.
    Type: Grant
    Filed: January 26, 2009
    Date of Patent: November 13, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Koji Fukuda, Hiroki Yamashita, Daisuke Hamano
  • Patent number: 8290107
    Abstract: A clock data recovery circuit that supplies stable reference clocks to the object respectively by shortening the time of bit synchronization with each received burst data signal regardless of jittering components included in the received burst data signal, includes an interpolator that generates a reference clock having the same frequency as that of a received burst data signal and two types of determination clocks having a phase that is different from that of the reference clock respectively; and a phase adjustment control circuit that can change the phase of the reference clock in units of M/2?. After beginning receiving of a burst data signal, the clock data recovery circuit sets a large phase change value at the first phase adjustment timing and reduces the change value in the second and subsequent phase adjustment timings, thereby realizing quick bit synchronization with the received burst data signal to generate a reference clock.
    Type: Grant
    Filed: January 27, 2009
    Date of Patent: October 16, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Masayuki Takase, Hideki Endo, Koji Fukuda, Kenichi Sakamoto
  • Publication number: 20120249217
    Abstract: A high-speed semiconductor integrated circuit device is achieved by adjusting an offset voltage. For example, dummy NMOS transistors MND1 (MND1a and MND1b) and MND2 (MND2a and MND2b) are connected to drain outputs of NMOS transistors MN1 and MN2 operated according to differential input signals Din_p and Din_n, respectively. The MND1 is arranged adjacent to the MN1, and a source of the MND1a and a drain of the MN1 share a diffusion layer. The MND2 is arranged adjacent to the MN2, and a source of the MND2a and a drain of the MN2 share a diffusion layer. The MND1 and the MND2 function as dummy transistors for suppressing variations in process of the MN1 and the MN2 and, and besides, they also function as means for adjusting the offset voltage by appropriately applying an offset-amount setting signal OFST to each gate to provide a capacitor to either the MN1 or the MN2.
    Type: Application
    Filed: October 4, 2010
    Publication date: October 4, 2012
    Inventors: Koji Fukuda, Hiroki Yamashita
  • Patent number: 8253461
    Abstract: There is provided a waveform equalization circuit with pulse width modulation that includes pulse-width adjust-level generation circuits PWCLC1a, PWCLC2a, for generating a pulse-width adjust-level VCNT on the basis of preceding input data units Din_P, Din_N, respectively, pulse-width adjustment circuits PWCC1a, PWCC2a, for adjusting a pulse-width according to VCNT, respectively, and a waveform shaping circuit WAC for shaping a waveform of an output signal from each of the pulse-width adjustment circuits. The pulse-width adjustment circuit has a driving power to be controlled according to a consecutive bits count of each of the preceding input data units, and varies transition time of each of output data units Do1_P, Do1_N, thereby adjusting the pulse width.
    Type: Grant
    Filed: June 29, 2010
    Date of Patent: August 28, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Fumio Yuki, Hiroki Yamashita, Koji Fukuda
  • Publication number: 20120133394
    Abstract: The invention relates to a clock generation circuit and a signal reproduction circuit including the clock generation circuit, and, more particularly, the invention provides a data judgment/phase comparison circuit capable of performing both of data judgment and phase comparison by a single-phase clock, and provides a CDR (Clock Data Recovery) circuit including the data judgment/phase comparison circuit. The same data and clock are inputted to two data judging units C GOOD and C BAD each having a different data determination period (setup/hold time) required for correctly judging a data, and an output of the data judging unit C GOOD having a shorter required data determination period is taken as a data output of the data judgment/phase comparison circuit. When the outputs of both of the data judging units are different from each other, a signal Early indicating that a clock phase is too early or a signal Late indicating that the clock phase is too late is outputted.
    Type: Application
    Filed: September 29, 2009
    Publication date: May 31, 2012
    Inventors: Koji Fukuda, Hiroki Yamashita
  • Patent number: 8149973
    Abstract: A clock recovery circuit capable of simultaneously satisfying all of a bit synchronization period, a clock wander tracking performance, and a high high-frequency jitter tolerance. The clock recovery circuit includes: a phase difference detecting circuit that detects a phase difference between an input data signal and a recovery clock; an averaging circuit that averages the output of the phase difference detecting circuit; a sampling and holding circuit with resetting that samples and holds the output of the phase difference detecting circuit; and a recovery clock generating circuit that generates a recovery clock having a phase corresponding to the sum of the integral value of the output of the averaging circuit and the output of the sampling and holding circuit with resetting. The sampling and holding circuit with resetting receives a burst transmission start signal and samples and holds the output of the phase difference detecting.
    Type: Grant
    Filed: January 29, 2009
    Date of Patent: April 3, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Koji Fukuda, Hiroki Yamashita