Abstract: A memory device includes a plurality of pages arrayed in a column direction in a plan view, each page being constituted by a plurality of memory cells arrayed in a row direction on a substrate. Each of the memory cells included in each of the pages includes a semiconductor base material, first and second impurity regions positioned at respective ends of the semiconductor base material, first, second, and third gate conductor layers. The first and second impurity regions, the first, second, and third gate conductor layers are connected to a source line, a bit line, a first select gate line, a plate line, and a second select gate line, respectively. Upon operation end of page write operation and page read operation, voltage of the plate line is set to negative voltage lower than 0 V through capacitive coupling of the plate line and each of the first and second select gate lines to improve data retention characteristics of a write memory cell.

Abstract: A memory device including a semiconductor element includes two stacked memory cells including a first impurity region, first and second gate conductor layers, a second impurity region, third and fourth gate conductor layers, and a third impurity region on a P layer substrate in order from below in a vertical direction and configured to perform data write, read, and erase operation with voltage applied to each gate conductor layer. The first impurity region is connected to a first bit line. One of the first and second gate conductor layers and the other are connected to a word line and a plate line, respectively. The third and fourth gate conductor layers are each connected to the word line or plate line connected to the second or first gate conductor layer, respectively. The second and third impurity regions are connected to a source line and a second bit line, respectively.

Abstract: A first N+ layer, a first P layer, a second N+ layer, a second P layer, and a third N+ layer are formed on a P layer substrate in order from below vertically, a first gate insulating layer surrounds the first P layer, a second gate insulating layer surrounds the second P layer, first and second gate conductor layers surround the first gate insulating layer, and third and fourth gate conductor layers surround the second gate insulating layer. A first wiring layer is connected to the first N+ layer, a second wiring layer is connected to the second N+ layer, and a third wiring layer is connected to the third N+ layer. The first and second gate conductor layers, the second wiring layer, and the third and fourth gate conductor layers have identical shapes in a plan view and are orthogonal to the first and third wiring layers.

Abstract: A memory device includes pages in a column direction on a substrate and memory cells in each page in a row direction in plan view. Each memory cell includes a semiconductor base, first and second impurity regions, connected to a source line and a bit line, respectively, at both ends of the semiconductor base, and first and second gate conductor layers, one of which is connected to a word line and the other of which is connected to a plate line. Page erase, page write, and read operations are performed by controlling voltages applied to the source, bit, word, and plate lines. A first operation of outputting data of a first page to an input/output circuit via a sense amplifier circuit and a second operation of reading data of a second page of the same bank as the first page to the bit line are performed in parallel.

Abstract: A memory device includes pages arranged in columns and each constituted by a plurality of memory cells on a substrate, voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity layer, and a second impurity layer in each memory cell included in each of the pages are controlled to perform a page write operation of retaining, inside a channel semiconductor layer, a group of positive holes generated by an impact ionization phenomenon or by a gate-induced drain leakage current, and the voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity layer, and the second impurity layer are controlled to perform a page erase operation of discharging the group of positive holes from inside the channel semiconductor layer.

Abstract: A memory device includes pages in a column direction on a substrate and memory cells in each page in a row direction in plan view. Each memory cell includes a semiconductor base, first and second impurity regions at both ends of the semiconductor base, and first and second gate conductor layers. A page erase operation, a page write operation, and a page read operation are performed by controlling voltages applied to the first and second impurity regions and the first and second gate conductor layers. In a first page group including at least one page, a refresh operation of increasing positive holes is performed in a memory cell storing logical data “1”. The refresh operation is performed continuously to an N-th page group.

Abstract: A memory device includes pages in a column direction on a substrate and memory cells in each page in a row direction in plan view. Each memory cell includes a semiconductor base, first and second impurity regions, connected to a source line and a bit line, respectively, at both ends of the semiconductor base, and first and second gate conductor layers, one of which is connected to a word line and the other of which is connected to a plate line. A continuous operation of a page erase operation and a page write operation is performed by controlling voltages applied to the source line, the bit line, the word line, and the plate line without performing a reset operation for returning the voltage applied to the plate line to a ground voltage.

Abstract: Si pillars 22a to 22d stand on an N+ layer 21 connected to a source line SL. Lower portions of the Si pillars 22a to 22d are surrounded by a HfO2 layer 25a, which is surrounded by TiN layers 26a and 26b that are respectively connected to plate lines PL1 and PL2 and are isolated from each other. Upper portions of the Si pillars 22a to 22d are surrounded by a HfO2 layer 25b, which is surrounded by TiN layers 28a and 28b that are respectively connected to word lines WL1 and WL2 and are isolated from each other. A thickness Lg1 of the TiN layer 26a on a line X-X? is smaller than twice a thickness Lg2 of the TiN layer 26a on a line Y-Y? and is larger than or equal to the thickness Lg2. The thickness Lg1 of the TiN layer 28a on the line X-X? is smaller than twice the thickness Lg2 of the TiN layer 28a on the line Y-Y?.

Abstract: A dynamic flash memory includes a p layer as a semiconductor base material, first and second n+ layers on opposite sides thereof, first and second gate insulating layers in contact with each other and partially covering the p layer, and first and second gate conductor layers electrically isolated from each other and respectively provided on the first and second gate insulating layers. The first and second n+ layers and first and second gate conductor layers are respectively connected to source, bit, word, and plate lines. During writing, 1.0 V, 1.5 V, and 1.2 V are sequentially applied to the bit, plate, and word lines, respectively. During erasing, 2 V is applied to the plate line, and then, a voltage applied to each terminal is always set 0 V or greater (e.g., 0.6 V for the bit line). Further, during reading, voltages are sequentially applied to the bit, plate, and word lines.

Abstract: A memory device includes pages, each being composed of a plurality of memory cells arrayed on a substrate in row form, and controls voltages to be applied to a first gate conductor layer, a second gate conductor layer, a first impurity layer, and a second impurity layer of each of the memory cells included in the pages to perform a page write operation of holding a hole group generated by an impact ionization phenomenon or a gate induced drain leakage current in a channel semiconductor layer, and controls voltages to be applied to the first gate conductor layer, the second gate conductor layer, the third gate conductor layer, the fourth gate conductor layer, the first impurity layer, and the second impurity layer to perform a page erase operation of removing the hole group out of the channel semiconductor layer.

Abstract: A memory device includes a page made up of plural memory cells arranged in a column on a substrate, and a page write operation is performed to hold positive hole groups generated by an impact ionization phenomenon, in a channel semiconductor layer by controlling voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity region, and a second impurity region of each memory cell contained in the page and a page erase operation is performed to remove the positive hole groups out of the channel semiconductor layer by controlling voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity region, and the second impurity region.

Abstract: A method of frequency-converting a received radio frequency (RF) signal includes frequency mixing a received RF signal with a first local oscillator (LO) signal to generate a first intermediate frequency (IF) signal, where the first IF signal is a mixed signal of a desired signal and an image signal. The method further includes frequency mixing the RF signal with a second LO signal to generate a second IF signal, where the second LO signal has a same frequency as the first LO signal, and the second LO signal has a 90 degree phase shift relative to the first LO signal.

Abstract: A non-aqueous electrolyte solution battery includes a positive electrode containing manganese dioxide and a carbon material; a negative electrode including one of lithium and a lithium alloy; a non-aqueous electrolyte solution; and a container configured to accommodate the positive electrode, the negative electrode, and the non-aqueous electrolyte solution. In a spectrum that is measured by performing Raman spectroscopic analysis with respect to the positive electrode by using argon laser at a wavelength of 514.5 nm, an average value of peak intensity ratios ID/IG of an intensity ID of a peak appearing in the vicinity of 1330 cm?1 to an intensity IG of a peak appearing in the vicinity of 1580 cm?1 satisfies a relationship of 0.5?ID/IG?1.3.

Abstract: A method of frequency-converting a received radio frequency (RF) signal includes frequency mixing a received RF signal with a first local oscillator (LO) signal to generate a first intermediate frequency (IF) signal, where the first IF signal is a mixed signal of a desired signal and an image signal. The method further includes frequency mixing the RF signal with a second LO signal to generate a second IF signal, where the second LO signal has a same frequency as the first LO signal, and the second LO signal has a 90 degree phase shift relative to the first LO signal.

Abstract: A control apparatus includes a controller that controls a motor, a first transmission channel connected to a first power-supply terminal of an alternating-current source that supplies an alternating-current voltage, a second transmission channel connected to a second power-supply terminal of the alternating-current source, and a third transmission channel connected to each of the first transmission channel and the second transmission channel. The controller switches the rotational speed of the motor based on the voltage value of a signal input to the controller in accordance with a first connection status of the first transmission channel and the third transmission channel and a second connection status of the second transmission channel and the third transmission channel.

Abstract: A gear shift control device for an automatic transmission device includes a transmission including an output unit setting and outputting a target value of the hydraulic pressure to the hydraulic control device. The output unit, when the shift stage is changed from a shift stage to another, increases the target value for a first friction coupling portion in the decoupled state in the shift stage to a first value, reduces to a second value, increases to a third value after the value is reduced to the second value, sets to a fourth value after the value is increased to the third value, and sets to a fifth value after the target value is set to the fourth value, and the output unit sets the fourth value according to magnitude of input torque to the transmission.

Abstract: A transmission control device is used in an automatic transmission device including a transmission gear having friction coupling portions that are changed between a coupled state and an uncoupled state, and configuring transmission stages corresponding to a combination of the coupled state and the uncoupled state, and a hydraulic control device. The device includes: a determination unit determining a change in the transmission stage; and an output unit setting a target value of the hydraulic pressure, and outputting the target value to the hydraulic control device. In a case where one transmission stage is changed to another, the output unit increases the target value to a first value for a first friction coupling portion in the uncoupled state in the one transmission stage, thereafter, to a second value smaller than the first value and maintaining the uncoupled state, and thereafter, to a third value greater than the second value.

Abstract: A transmission control device is used in an automatic transmission device including a transmission gear having friction coupling portions that are changed between a coupled state and an uncoupled state, and configuring transmission stages corresponding to a combination of the coupled state and the uncoupled state, and a hydraulic control device. The device includes: a determination unit determining a change in the transmission stage; and an output unit setting a target value of the hydraulic pressure, and outputting the target value to the hydraulic control device. In a case where one transmission stage is changed to another, the output unit increases the target value to a first value for a first friction coupling portion in the uncoupled state in the one transmission stage, thereafter, to a second value smaller than the first value and maintaining the uncoupled state, and thereafter, to a third value greater than the second value.

Abstract: A gear shift control device for an automatic transmission device includes a transmission including an output unit setting and outputting a target value of the hydraulic pressure to the hydraulic control device. The output unit, when the shift stage is changed from a shift stage to another, increases the target value for a first friction coupling portion in the decoupled state in the shift stage to a first value, reduces to a second value, increases to a third value after the value is reduced to the second value, sets to a fourth value after the value is increased to the third value, and sets to a fifth value after the target value is set to the fourth value, and the output unit sets the fourth value according to magnitude of input torque to the transmission.

Abstract: According to a surface defect inspection device and a surface defect inspection method according to the present invention, an inspection face of an inspection object is irradiated with illumination light, and a defect at the inspection face is detected, based on an image including the inspection face captured. According to the surface defect inspection device and the surface defect inspection method, the illumination light is emitted with formation of at least one set of a light region and a dark region, and a range of a defect detection image region for the detection of the defect, to be set to the image capturing the inspection face irradiated with the illumination light in the light region, is adjusted in accordance with a previously defined degree of visibility for orange peel, at the detection of the defect at the inspection face.