Patents by Inventor Koji Hiraiwa
Koji Hiraiwa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8409998Abstract: According to a method of manufacturing a vertical-cavity surface-emitting semiconductor laser element in accordance with the present invention, a process of wet etching is performed for a part that is oxidized in a layer of an AlGaAs (42) which configures a layer having an index of refraction as lower and in which a composition of aluminum is designed to be as higher comparing to the other pairs of layers in a DBR mirror at an upper side that are formed at an inner side of a mesa post (38). And then a process of filling up again is performed with making use of a layer of polyimide (26). Moreover, an etchant that includes such as a hydrofluoric acid or a buffered hydrofluoric acid or an aqueous ammonia or the like is made use in order to perform such the process of wet etching.Type: GrantFiled: September 30, 2009Date of Patent: April 2, 2013Assignee: Furukawa Electric Co., LtdInventors: Kageyama Takeo, Norihiro Iwai, Koji Hiraiwa, Yoshihiko Ikenaga
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Patent number: 8270447Abstract: A semiconductor light emitting element, comprises: an active layer; a first electrode and second electrode that inject current to the active layer; a semiconductor layer between the active layer and the first electrode; and a dielectric layer that is provided on the semiconductor layer and through which light from the active layer passes; wherein the first electrode is provided on the semiconductor layer, has an opening through which light from the active layer passes, and comprises a first electrode layer that comes in contact with and is provided on the semiconductor layer, and a second electrode layer that is provided on the first electrode layer, with the first electrode layer having less reactivity with the semiconductor layer than the second electrode layer; and the dielectric layer is provided inside the opening such that the end section on the opening side of the first electrode layer extends from the top of the semiconductor layer to the top of the dielectric layer.Type: GrantFiled: January 7, 2010Date of Patent: September 18, 2012Assignee: Furukawa Electric Co., Ltd.Inventors: Naoki Tsukiji, Norihiro Iwai, Keishi Takaki, Koji Hiraiwa
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Patent number: 8204093Abstract: A method of manufacturing a surface emitting laser element of a vertical cavity type comprises sequential accumulation that accumulates a reflecting mirror of a multilayered film layer at a lower side of the substrate, and accumulates semiconductor layers onto the reflecting minor at the lower side that comprises an active layer and a contact layer. The process includes forming a first layer of dielectric substance on the contact layer, forming an electrode of an annular shape on the contact layer that has an open part to be arranged for the first layer at an inner side of the open part, and forming a second layer of dielectric substance to cover the first layer and a gap formed between the first layer and the electrode of the annular shape. The accumulated semiconductor layers are etched to form a mesa post, using the electrode of the annular shape as a mask.Type: GrantFiled: September 16, 2009Date of Patent: June 19, 2012Assignee: The Furukawa Electric Co., Ltd.Inventors: Keishi Takaki, Norihiro Iwai, Koji Hiraiwa
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Patent number: 8178364Abstract: A method of performing a wafer level burn-in test for a plurality of surface-emitting laser devices formed on a wafer includes causing a plurality of contact electrodes arranged in a same plane with a pitch same as that of the surface-emitting laser devices being electrically connected to each other to have contact with pad electrodes of the surface-emitting laser devices, respectively, and applying a current to second electrodes of the surface-emitting laser devices and the contact electrodes. The wafer level burn-in test is performed while heating the wafer at a predetermined temperature. Laser lights emitted from the surface-emitting laser devices are monitored during the wafer level burn-in test.Type: GrantFiled: June 8, 2010Date of Patent: May 15, 2012Assignee: Furukawa Electric Co., Ltd.Inventors: Koji Hiraiwa, Takeo Kageyama, Norihiro Iwai, Keishi Takaki
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Publication number: 20110076854Abstract: According to a method of manufacturing a vertical-cavity surface-emitting semiconductor laser element in accordance with the present invention, a process of wet etching is performed for a part that is oxidized in a layer of an AlGaAs (42) which configures a layer having an index of refraction as lower and in which a composition of aluminum is designed to be as higher comparing to the other pairs of layers in a DBR mirror at an upper side that are formed at an inner side of a mesa post (38). And then a process of filling up again is performed with making use of a layer of polyimide (26). Moreover, an etchant that includes such as a hydrofluoric acid or a buffered hydrofluoric acid or an aqueous ammonia or the like is made use in order to perform such the process of wet etching.Type: ApplicationFiled: September 30, 2009Publication date: March 31, 2011Applicant: FURUKAWA ELECTRIC CO., LTD.Inventors: Kageyama Takeo, Norihiro Iwai, Koji Hiraiwa, Yoshihiko Ikenaga
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Publication number: 20110064108Abstract: A method of manufacturing a surface emitting laser element of a vertical cavity type in accordance with the present invention is characterized in that comprises the following steps of: applying a process of accumulations on a substrate, the process sequentially including accumulating a reflecting mirror of a multilayered film layer at a lower side thereof on to the substrate, and accumulating layers of a semiconductor as a plurality thereof on to the reflecting mirror of the multilayered film layer at the lower side thereof, that comprises an active layer and that further comprises a contact layer at a top layer thereof as well; forming a first layer of a dielectric substance as a process of a formation of the first layer of the dielectric substance at a part of regions on the contact layer; forming an electrode of an annular shape as a process of a formation of the electrode of the annular shape on the contact layer, that has an open part at a center thereof, in order to be arranged for the first layer of thType: ApplicationFiled: September 16, 2009Publication date: March 17, 2011Applicant: FURUKAWA ELECTRIC CO., LTD.Inventors: Keishi Takaki, Norihiro Iwai, Koji Hiraiwa
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Patent number: 7885307Abstract: A vertical-cavity surface-emitting (VCSEL) device has a layer structure including a top DBR mirror, an active layer, a current confinement oxide layer, and a bottom DBR mirror, the layer structure being configured as a mesa post. The current confinement oxide layer has a central current injection area and a peripheral current blocking area oxidized from the sidewall of the mesa post. The mesa post has a substantially square cross-sectional shape, thereby allowing an oxidation heat treatment to configure a substantially circular current injection area in the current-confinement oxide layer.Type: GrantFiled: October 19, 2006Date of Patent: February 8, 2011Assignee: The Furukawa Electric Co., Ltd.Inventors: Kinuka Tanabe, Yoshihiko Ikenaga, Norihiro Iwai, Takeo Kageyama, Koji Hiraiwa, Hirokazu Yoshikawa
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Publication number: 20110003403Abstract: A method of performing a wafer level burn-in test for a plurality of surface-emitting laser devices formed on a wafer includes causing a plurality of contact electrodes arranged in a same plane with a pitch same as that of the surface-emitting laser devices being electrically connected to each other to have contact with pad electrodes of the surface-emitting laser devices, respectively, and applying a current to second electrodes of the surface-emitting laser devices and the contact electrodes. The wafer level burn-in test is performed while heating the wafer at a predetermined temperature. Laser lights emitted from the surface-emitting laser devices are monitored during the wafer level burn-in test.Type: ApplicationFiled: June 8, 2010Publication date: January 6, 2011Applicant: THE FURUKAWA ELECTRIC CO., LTDInventors: Koji HIRAIWA, Takeo Kageyama, Norihiro Iwai, Keishi Takaki
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Publication number: 20100232465Abstract: A semiconductor light emitting element, comprises: an active layer; a first electrode and second electrode that inject current to the active layer; a semiconductor layer between the active layer and the first electrode; and a dielectric layer that is provided on the semiconductor layer and through which light from the active layer passes; wherein the first electrode is provided on the semiconductor layer, has an opening through which light from the active layer passes, and comprises a first electrode layer that comes in contact with and is provided on the semiconductor layer, and a second electrode layer that is provided on the first electrode layer, with the first electrode layer having less reactivity with the semiconductor layer than the second electrode layer; and the dielectric layer is provided inside the opening such that the end section on the opening side of the first electrode layer extends from the top of the semiconductor layer to the top of the dielectric layer.Type: ApplicationFiled: January 7, 2010Publication date: September 16, 2010Applicant: FURUKAWA ELECTRIC CO., LTDInventors: Naoki TSUKIJI, Norihiro IWAI, Keishi TAKAKI, Koji HIRAIWA
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Publication number: 20080273569Abstract: A VCSEL device includes a polyimide having a larger thickness (d1) on the surface of a semiconductor layer structure in a peripheral area 54, which is separated from a mesapost by an annular groove 52. The top surface of the central mesapost 30 is located at a lower position compared to the top surface of the peripheral area 54. A structure is obtained wherein the mesapost is not contacted by a jig or probe during handling the device in the test or assembly thereof.Type: ApplicationFiled: July 2, 2008Publication date: November 6, 2008Applicant: The Furukawa Electric Co, Ltd.Inventors: Koji HIRAIWA, Takeo Kageyama, Norihiro Iwai, Keishi Takaki
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Patent number: 7418020Abstract: A VCSEL device includes a polyimide having a larger thickness (d1) on the surface of a semiconductor layer structure in a peripheral area 54, which is separated from a mesapost by an annular groove 52. The top surface of the central mesapost 30 is located at a lower position compared to the top surface of the peripheral area 54. A structure is obtained wherein the mesapost is not contacted by a jig or probe during handling the device in the test or assembly thereof.Type: GrantFiled: October 31, 2006Date of Patent: August 26, 2008Assignee: The Furukawa Electric Co., Ltd.Inventors: Koji Hiraiwa, Takeo Kageyama, Norihiro Iwai, Keishi Takaki
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Publication number: 20070110115Abstract: A VCSEL device includes a polyimide having a larger thickness (d1) on the surface of a semiconductor layer structure in a peripheral area 54, which is separated from a mesapost by an annular groove 52. The top surface of the central mesapost 30 is located at a lower position compared to the top surface of the peripheral area 54. A structure is obtained wherein the mesapost is not contacted by a jig or probe during handling the device in the test or assembly thereof.Type: ApplicationFiled: October 31, 2006Publication date: May 17, 2007Applicant: The Furukawa Electric Co, Ltd.Inventors: Koji HIRAIWA, Takeo Kageyama, Norihiro Iwai, Keishi Takaki
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Publication number: 20070091965Abstract: A vertical-cavity surface-emitting (VCSEL) device has a layer structure including a top DBR mirror, an active layer, a current confinement oxide layer, and a bottom DBR mirror, the layer structure being configured as a mesa post. The current confinement oxide layer has a central current injection area and a peripheral current blocking area oxidized from the sidewall of the mesa post. The mesa post has a substantially square cross-sectional shape, thereby allowing an oxidation heat treatment to configure a substantially circular current injection area in the current-confinement oxide layer.Type: ApplicationFiled: October 19, 2006Publication date: April 26, 2007Applicant: FURUKAWA ELECTRIC CO., LTD.Inventors: Kinuka Tanabe, Yoshihiko Ikenaga, Norihiro Iwai, Takeo Kageyama, Koji Hiraiwa, Hirokazu Yoshikawa
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Patent number: 6177710Abstract: A semiconductor waveguide type photo detector capable of preventing leak current from occurring and excellent in dark current characteristics, and a manufacturing method thereof are provided.Type: GrantFiled: April 27, 1998Date of Patent: January 23, 2001Assignee: The Furukawa Electric Co., Ltd.Inventors: Kazuaki Nishikata, Koji Hiraiwa
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Patent number: 4970047Abstract: A fuel assembly for a nuclear reactor comprises a fuel bundle in which a number of fuel rods are regularly arranged and a channel box surrounding the outer periphery of the fuel bundle. The interior of the channel box is designed so that the inner cross sectional area of the channel box increases from the upstream side of the coolant flow towards the downstream side thereof, for example, by stepwisely shaving the inner surface of the channel box. The corner portions of the channel box may be chamfered to improve the stress due to the inner pressure.Type: GrantFiled: October 13, 1988Date of Patent: November 13, 1990Assignee: Kabushiki Kaisha ToshibaInventors: Makoto Ueda, Toru Mitsutake, Koichi Sakurada, Koji Hiraiwa, Yasuhiro Hattori, Mamoru Nagano, Hironori Echigoya