Patents by Inventor Koji Hosoe

Koji Hosoe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11173867
    Abstract: An airbag for a passenger seat adapted to be stored in a storage which is disposed in an instrument panel in front of a passenger seat is disclosed. The airbag includes a passenger-side wall which is disposed in a rear portion of the airbag as deployed for arresting a passenger, and a vehicle-side wall that extends from an outer circumferential edge of the passenger-side wall towards a front end of the airbag as deployed in a narrowing fashion for mounting on the storage by the front end. The vehicle-side wall includes a recessed area for circumventing an adjoining object disposed in the vehicle when deployed. The recessed area is composed of a tuck formed in a base member of the vehicle-side wall. The tuck is formed by jointing one or more pair of tuck jointing portions that are distant from one another in the base member as laid flat.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: November 16, 2021
    Assignee: TOYODA GOSEI CO., LTD.
    Inventor: Koji Hosoe
  • Publication number: 20210031716
    Abstract: A passenger seat airbag device includes an airbag including a front collision restraining surface, and an oblique collision restraining portion including a protruding portion in which a surface is set as an oblique collision restraining surface, and a restraining recess portion whose facing surfaces are able to restrain the head of the occupant. The rear wall main portion has the front collision restraining surface. The rear wall end edge portion has the oblique collision restraining surface. The upper edge of the rear wall end edge portion is coupled to a rear edge of the upper wall portion. The lower edge of the rear wall end edge portion is coupled to a rear edge of the lower wall portion. An entire edge of the separation edge of the rear wall end edge portion is coupled to a rear edge of the rear edge side portion.
    Type: Application
    Filed: July 8, 2020
    Publication date: February 4, 2021
    Inventors: Takuya HIRAIWA, Shinichi ISHIDA, Koji HOSOE, Masashi BABA, Ryo KUMAZAKI, Hiromi KONDO
  • Publication number: 20200247350
    Abstract: An airbag for a passenger seat adapted to be stored in a storage which is disposed in an instrument panel in front of a passenger seat is disclosed. The airbag includes a passenger-side wall which is disposed in a rear portion of the airbag as deployed for arresting a passenger, and a vehicle-side wall that extends from an outer circumferential edge of the passenger-side wall towards a front end of the airbag as deployed in a narrowing fashion for mounting on the storage by the front end. The vehicle-side wall includes a recessed area for circumventing an adjoining object disposed in the vehicle when deployed. The recessed area is composed of a tuck formed in a base member of the vehicle-side wall. The tuck is formed by jointing one or more pair of tuck jointing portions that are distant from one another in the base member as laid flat.
    Type: Application
    Filed: January 9, 2020
    Publication date: August 6, 2020
    Inventor: Koji HOSOE
  • Patent number: 10248479
    Abstract: The arithmetic processing device includes a first memory control unit configured to control an access to a first memory, a second memory control unit configured to control an access to a second memory. The arithmetic processing device further includes a diagnostic control unit configured to sequentially diagnose parts within the first memory via the first memory control unit, and configured to sequentially store in the second memory via the second memory control unit, diagnostic results of sequentially diagnosing the parts in parallel with the diagnosing the parts via the first memory control unit.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: April 2, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Makoto Suga, Akio Tokoyoda, Masatoshi Aihara, Koji Hosoe, Koichiro Takayama
  • Publication number: 20180336132
    Abstract: An apparatus includes a memory; and a processor that includes a memory-controller that controls transmission-and-reception of information to and from the memory, wherein the memory-controller comprises a buffer that includes storage-regions, a control-circuit that stores, in one of the storage-regions, information that operates the memory among pieces of information transmitted to the memory, a counter that counts a number of pieces of second information transmitted to the memory, the second information being information transmitted to the memory since the information is transmitted to the memory until the next information is transmitted to the memory and indicating no-transmission of the information, a second buffer that includes a second storage-regions respectively corresponding to the storage-regions, and a second control-circuit that stores a count value of the counter in one of the second storage-regions in association with the information stored in the storage region.
    Type: Application
    Filed: May 18, 2018
    Publication date: November 22, 2018
    Applicant: FUJITSU LIMITED
    Inventors: Makoto SUGA, Koji HOSOE, Masatoshi Aihara
  • Patent number: 10078602
    Abstract: An information processing apparatus includes: a memory device configured to store data; an arithmetic processor configured to issue a request to be transmitted to the memory device; and a memory controller including: a buffer configured to store one or more unselected requests that are issued by the arithmetic processing processor and are not selected; a history register configured to hold one or more addresses for one or more transmitted requests that have been transmitted to the memory device; and a selection unit configured to select, from the one or more unselected requests stored in the buffer, a target request to be transmitted to the memory device based on the one or more addresses stored in the history register and transmit the target request to the memory device.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: September 18, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Akio Tokoyoda, Masatoshi Aihara, Koichiro Takayama, Koji Hosoe
  • Patent number: 10002092
    Abstract: An arithmetic processing unit including a memory controller configured to make variable-length access requests allowing a plurality of lengths to a memory, the memory controller comprising: a plurality of buffers configured to hold the access requests for each of the lengths of the access requests; and an arbitrator configured to select one of access requests stored in the plurality of buffers in accordance with a number of remaining resources of the memory.
    Type: Grant
    Filed: August 12, 2014
    Date of Patent: June 19, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Yuta Toyoda, Koji Hosoe, Akio Tokoyoda, Masatoshi Aihara, Makoto Suga
  • Patent number: 9785579
    Abstract: A memory controller has a request holding unit holding a write request and a read request; a transmission unit transmitting any one of the write request and the read request to a memory through a transmission bus; a reception unit receiving read data corresponding to the read request through a reception bus; and a request arbitration unit performing: a first processing of transmitting the write request before the read request, when a first reception time is not later than a second reception time, and a second processing of transmitting the read request before the write request, when the first reception time is later than the second reception time. The first reception time is when reception of the read data is started when the write request is transmitted first, and the second reception time is when the reception of the read data is started when the read request is transmitted first.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: October 10, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Yuta Toyoda, Koji Hosoe, Akio Tokoyoda, Masatoshi Aihara, Makoto Suga
  • Patent number: 9766820
    Abstract: An arithmetic processing device which connects to a main memory, the arithmetic processor includes a cache memory which stores data, an arithmetic unit which performs an arithmetic operation for data stored in the cache memory, a first control device which controls the cache memory and outputs a first request which reads the data stored in the main memory, and a second control device which is connected to the main memory and transmits a plurality of second requests which are divided the first request output from the first control device, receives data corresponding to the plurality of second requests which is transmitted from the main memory and sends each of the data to the first control device.
    Type: Grant
    Filed: May 11, 2015
    Date of Patent: September 19, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Yuta Toyoda, Koji Hosoe, Masatoshi Aihara, Akio Tokoyoda, Makoto Suga
  • Patent number: 9645818
    Abstract: The information processing apparatus includes an arithmetic processing device configured to output an access request, a storage device configured to store data, a storage control device configured to accept the access request to the storage device from the arithmetic processing device, transfer the accepted access request to the storage device, and acquire a response to the access request from the storage device, and a diagnosis control device configured to send an access request to the storage device to the storage control device in place of the access request to the storage device from the arithmetic processing device, and acquire a response from the storage device via the storage control device.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: May 9, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Makoto Suga, Koji Hosoe, Akio Tokoyoda, Masatoshi Aihara, Yuta Toyoda
  • Patent number: 9619347
    Abstract: An apparatus includes: a physical-layer device that distributes data to first lanes and performs data transfer to/from an external device by second lanes each of which has a number of the first lanes; and a transfer circuit that transfers data output by a central-processing unit performing arithmetic-processing to the physical-layer device and transfers the data received from the physical-layer device and received by the central-processing unit, the transfer circuit that comprises an information-acquisition unit that receives one of detection information of the first lanes which indicates that the physical-layer device has received data from the external device and error information of the first lanes which indicates that the data transferred to the physical-layer device from the external device has an error, from the physical-layer device, and a selection unit configured to specify the second lane to be degenerated based on one of the error information and the detection information.
    Type: Grant
    Filed: February 24, 2015
    Date of Patent: April 11, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Masahiro Maeda, Tomohiro Inoue, Shinya Hiramoto, Shun Ando, Koji Hosoe, Yuichiro Ajima
  • Patent number: 9612891
    Abstract: A memory controller is provided between a CPU and a main memory, controls access from the CPU to the main memory, and includes a data storage area and a controller. In a case where error information indicating that an error occurs is included in write data from the CPU to the main memory, the controller stores the write data in a data storage area in association with a writing destination address. Therefore, even in a case where the error information is not written in the main memory, the error information can be recorded.
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: April 4, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Akio Tokoyoda, Yuta Toyoda, Makoto Suga, Masatoshi Aihara, Koji Hosoe
  • Publication number: 20160350196
    Abstract: The arithmetic processing device includes a first memory control unit configured to control an access to a first memory, a second memory control unit configured to control an access to a second memory. The arithmetic processing device further includes a diagnostic control unit configured to sequentially diagnose parts within the first memory via the first memory control unit, and configured to sequentially store in the second memory via the second memory control unit, diagnostic results of sequentially diagnosing the parts in parallel with the diagnosing the parts via the first memory control unit.
    Type: Application
    Filed: May 10, 2016
    Publication date: December 1, 2016
    Applicant: FUJITSU LIMITED
    Inventors: Makoto SUGA, AKIO TOKOYODA, Masatoshi Aihara, Koji HOSOE, KOICHIRO TAKAYAMA
  • Publication number: 20160342541
    Abstract: An information processing apparatus includes: a memory device configured to store data; an arithmetic processor configured to issue a request to be transmitted to the memory device; and a memory controller including: a buffer configured to store one or more unselected requests that are issued by the arithmetic processing processor and are not selected; a history register configured to hold one or more addresses for one or more transmitted requests that have been transmitted to the memory device; and a selection unit configured to select, from the one or more unselected requests stored in the buffer, a target request to be transmitted to the memory device based on the one or more addresses stored in the history register and transmit the target request to the memory device.
    Type: Application
    Filed: April 11, 2016
    Publication date: November 24, 2016
    Applicant: FUJITSU LIMITED
    Inventors: Akio Tokoyoda, Masatoshi Aihara, Koichiro Takayama, Koji Hosoe
  • Publication number: 20160110193
    Abstract: The information processing apparatus includes an arithmetic processing device configured to output an access request, a storage device configured to store data, a storage control device configured to accept the access request to the storage device from the arithmetic processing device, transfer the accepted access request to the storage device, and acquire a response to the access request from the storage device, and a diagnosis control device configured to send an access request to the storage device to the storage control device in place of the access request to the storage device from the arithmetic processing device, and acquire a response from the storage device via the storage control device.
    Type: Application
    Filed: September 29, 2015
    Publication date: April 21, 2016
    Inventors: Makoto Suga, Koji Hosoe, Akio Tokoyoda, Masatoshi Aihara, Yuta Toyoda
  • Publication number: 20160098212
    Abstract: An information processor apparatus includes: a storage device to perform processing based on a read request or a write request and output a response after completing the processing; an arithmetic processor to output the read and write requests to the storage device; and a control device, including paths, to control the storage device; the control device: receives the read request or the write request from the arithmetic processor; acquires, for each of the paths, an overall time until the response to a transmitted read and write requests is received based on a first number of the transmitted read requests and a second number of the transmitted write requests, selects a used path based on the overall time; transmits the read request or the write request through the used path to the storage device; and receives the response to the read request or the write request through the used path.
    Type: Application
    Filed: September 8, 2015
    Publication date: April 7, 2016
    Inventors: AKIO TOKOYODA, Koji HOSOE, Masatoshi Aihara, Yuta Toyoda, Makoto SUGA
  • Publication number: 20150339062
    Abstract: An arithmetic processing device which connects to a main memory, the arithmetic processor includes a cache memory which stores data, an arithmetic unit which performs an arithmetic operation for data stored in the cache memory, a first control device which controls the cache memory and outputs a first request which reads the data stored in the main memory, and a second control device which is connected to the main memory and transmits a plurality of second requests which are divided the first request output from the first control device, receives data corresponding to the plurality of second requests which is transmitted from the main memory and sends each of the data to the first control device.
    Type: Application
    Filed: May 11, 2015
    Publication date: November 26, 2015
    Inventors: Yuta Toyoda, Koji HOSOE, Masatoshi Aihara, AKIO TOKOYODA, Makoto SUGA
  • Publication number: 20150278043
    Abstract: An apparatus includes: a physical-layer device that distributes data to first lanes and performs data transfer to/from an external device by second lanes each of which has a number of the first lanes; and a transfer circuit that transfers data output by a central-processing unit performing arithmetic-processing to the physical-layer device and transfers the data received from the physical-layer device and received by the central-processing unit, the transfer circuit that comprises an information-acquisition unit that receives one of detection information of the first lanes which indicates that the physical-layer device has received data from the external device and error information of the first lanes which indicates that the data transferred to the physical-layer device from the external device has an error, from the physical-layer device, and a selection unit configured to specify the second lane to be degenerated based on one of the error information and the detection information.
    Type: Application
    Filed: February 24, 2015
    Publication date: October 1, 2015
    Applicant: FUJITSU LIMITED
    Inventors: Masahiro Maeda, Tomohiro Inoue, Shinya Hiramoto, Shun Ando, Koji HOSOE, Yuichiro Ajima
  • Publication number: 20150149746
    Abstract: An arithmetic processing device promotes transmission efficiency between a processor and a memory. The arithmetic processing device has an arithmetic processing unit which issues an instruction accompanying with data which is sent to the memory, a judgment unit which judges whether or not a redundancy degree of the data which is accompanied with the instruction is more than a predetermined value, a compression unit which judges whether or not compress the data based on an waiting time and a compression time when the redundancy degree of the data is more than the predetermined value, and compress the data when judging that performs the compression, and an instruction arbitration unit which transfers the instruction accompanying with the compressed data to the memory when the compression unit performs the compression and transfers the instruction accompanying with the non-compressed data to the memory when the compression unit does not perform the compression.
    Type: Application
    Filed: November 10, 2014
    Publication date: May 28, 2015
    Inventors: Makoto SUGA, AKIO TOKOYODA, Koji HOSOE, Masatoshi Aihara, Yuta Toyoda
  • Publication number: 20150149675
    Abstract: A memory controller has a request holding unit holding a write request and a read request; a transmission unit transmitting any one of the write request and the read request to a memory through a transmission bus; a reception unit receiving read data corresponding to the read request through a reception bus; and a request arbitration unit performing: a first processing of transmitting the write request before the read request, when a first reception time is not later than a second reception time, and a second processing of transmitting the read request before the write request, when the first reception time is later than the second reception time. The first reception time is when reception of the read data is started when the write request is transmitted first, and the second reception time is when the reception of the read data is started when the read request is transmitted first.
    Type: Application
    Filed: November 17, 2014
    Publication date: May 28, 2015
    Inventors: Yuta Toyoda, Koji HOSOE, AKIO TOKOYODA, Masatoshi Aihara, Makoto SUGA