Patents by Inventor Koji Koike

Koji Koike has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240120646
    Abstract: There is provided a metal plate antenna transmitting and receiving wireless signals conforming to a prescribed communication standard, wherein an antenna width is designed to satisfy radiation resistance achieving a prescribed standing wave ratio in a resonant mode in which a loop length of the metal plate antenna is 1.5 wavelength of a wireless signal conforming to the prescribed communication standard.
    Type: Application
    Filed: September 6, 2023
    Publication date: April 11, 2024
    Applicant: KABUSHIKI KAISHA TOKAI RIKA DENKI SEISAKUSHO
    Inventors: Koji INAFUNE, Kenichi KOGA, Tatsuya KOIKE, Satoshi MORI
  • Patent number: 8841753
    Abstract: A semiconductor device includes: an interlayer insulating film formed on a substrate; a wiring formed in the interlayer insulating film in a chip region of the substrate; a seal ring formed in the interlayer insulating film in a periphery of the chip region and continuously surrounding the chip region; and a first protective film formed on the interlayer insulating film having the wiring and the seal ring formed therein. A first opening is formed in the first protective film in a region located outside the seal ring when viewed from the chip region, and the interlayer insulating film is exposed in the first opening.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: September 23, 2014
    Assignee: Panasonic Corporation
    Inventors: Koji Takemura, Hiroshige Hirano, Yutaka Itoh, Hikari Sano, Koji Koike
  • Patent number: 8810039
    Abstract: A semiconductor device includes: a semiconductor substrate; a first interlayer insulating film formed over the semiconductor substrate; a pad formed above the first interlayer insulating film; and a plurality of first interconnects spaced apart from each other in a portion of the first interlayer insulating film located below the pad. Below the pad, the first interconnects are formed in quadrangular plan shapes.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: August 19, 2014
    Assignee: Panasonic Corporation
    Inventors: Koji Takemura, Hiroshige Hirano, Masao Takahashi, Hikari Sano, Yutaka Itoh, Koji Koike
  • Patent number: 8237281
    Abstract: A semiconductor device includes at least three or more wiring layers stacked in an interlayer insulating film on a semiconductor substrate, a seal ring provided at the outer periphery of a chip region of the semiconductor substrate and a chip strength reinforcement provided in part of the chip region near the seal ring. The chip strength reinforcement is made of a plurality of dummy wiring structures and each of the plurality of dummy wiring structures is formed to extend across and within two or more of the wiring layers including one or none of the bottommost wiring layer and the topmost wiring layer using a via portion.
    Type: Grant
    Filed: January 4, 2011
    Date of Patent: August 7, 2012
    Assignee: Panasonic Corporation
    Inventors: Koji Takemura, Hiroshige Hirano, Yutaka Itoh, Hikari Sano, Masao Takahashi, Koji Koike
  • Publication number: 20120181670
    Abstract: A semiconductor device includes: an interlayer insulating film formed on a substrate; a wiring formed in the interlayer insulating film in a chip region of the substrate; a seal ring formed in the interlayer insulating film in a periphery of the chip region and continuously surrounding the chip region; and a first protective film formed on the interlayer insulating film having the wiring and the seal ring formed therein. A first opening is formed in the first protective film in a region located outside the seal ring when viewed from the chip region, and the interlayer insulating film is exposed in the first opening.
    Type: Application
    Filed: March 23, 2012
    Publication date: July 19, 2012
    Applicant: Panasonic Corporation
    Inventors: Koji TAKEMURA, Hiroshige Hirano, Yutaka Itoh, Hikari Sano, Koji Koike
  • Patent number: 8164163
    Abstract: A semiconductor device includes: an interlayer insulating film formed on a substrate; a wiring formed in the interlayer insulating film in a chip region of the substrate; a seal ring formed in the interlayer insulating film in a periphery of the chip region and continuously surrounding the chip region; and a first protective film formed on the interlayer insulating film having the wiring and the seal ring formed therein. A first opening is formed in the first protective film in a region located outside the seal ring when viewed from the chip region, and the interlayer insulating film is exposed in the first opening.
    Type: Grant
    Filed: February 12, 2008
    Date of Patent: April 24, 2012
    Assignee: Panasonic Corporation
    Inventors: Koji Takemura, Hiroshige Hirano, Yutaka Itoh, Hikari Sano, Koji Koike
  • Publication number: 20120080780
    Abstract: A semiconductor device includes: a semiconductor substrate; a first interlayer insulating film formed over the semiconductor substrate; a pad formed above the first interlayer insulating film; and a plurality of first interconnects spaced apart from each other in a portion of the first interlayer insulating film located below the pad. Below the pad, the first interconnects are formed in quadrangular plan shapes.
    Type: Application
    Filed: December 12, 2011
    Publication date: April 5, 2012
    Applicant: Panasonic Corporation
    Inventors: Koji TAKEMURA, Hiroshige Hirano, Masao Takahashi, Hikari Sano, Yutaka Itoh, Koji Koike
  • Patent number: 8102056
    Abstract: A semiconductor device includes: a semiconductor substrate; a first interlayer insulating film formed over the semiconductor substrate; a pad formed above the first interlayer insulating film; and a plurality of first interconnects spaced apart from each other in a portion of the first interlayer insulating film located below the pad. Below the pad, the first interconnects are formed in quadrangular plan shapes.
    Type: Grant
    Filed: August 29, 2006
    Date of Patent: January 24, 2012
    Assignee: Panasonic Corporation
    Inventors: Koji Takemura, Hiroshige Hirano, Masao Takahashi, Hikari Sano, Yutaka Itoh, Koji Koike
  • Patent number: 8044482
    Abstract: A semiconductor device includes an insulating film formed on a semiconductor substrate, a contact wiring formed in the insulating film, a protective film formed on the contact wiring and the insulating film, an opening portion formed in the protective film, the contact wiring being exposed through the opening portion, and an electrode pad formed in the opening portion, the electrode pad being electrically connected to the contact wiring. A region where the contact wiring is not provided is present below the opening portion.
    Type: Grant
    Filed: August 12, 2009
    Date of Patent: October 25, 2011
    Assignee: Panasonic Corporation
    Inventors: Yukitoshi Ota, Hiroshige Hirano, Yutaka Itou, Koji Koike
  • Publication number: 20110095430
    Abstract: A semiconductor device includes at least three or more wiring layers stacked in an interlayer insulating film on a semiconductor substrate, a seal ring provided at the outer periphery of a chip region of the semiconductor substrate and a chip strength reinforcement provided in part of the chip region near the seal ring. The chip strength reinforcement is made of a plurality of dummy wiring structures and each of the plurality of dummy wiring structures is formed to extend across and within two or more of the wiring layers including one or none of the bottommost wiring layer and the topmost wiring layer using a via portion.
    Type: Application
    Filed: January 4, 2011
    Publication date: April 28, 2011
    Applicant: PANASONIC CORPORATION
    Inventors: Koji TAKEMURA, Hiroshige Hirano, Yutaka Itoh, Hikari Sano, Masao Takahashi, Koji Koike
  • Patent number: 7888801
    Abstract: A semiconductor device includes at least three or more wiring layers stacked in an interlayer insulating film on a semiconductor substrate, a seal ring provided at the outer periphery of a chip region of the semiconductor substrate and a chip strength reinforcement provided in part of the chip region near the seal ring. The chip strength reinforcement is made of a plurality of dummy wiring structures and each of the plurality of dummy wiring structures is formed to extend across and within two or more of the wiring layers including one or none of the bottommost wiring layer and the topmost wiring layer using a via portion.
    Type: Grant
    Filed: April 27, 2009
    Date of Patent: February 15, 2011
    Assignee: Panasonic Corporation
    Inventors: Koji Takemura, Hiroshige Hirano, Yutaka Itoh, Hikari Sano, Masao Takahashi, Koji Koike
  • Patent number: 7789222
    Abstract: An endless dough conveyor 16 is provided with a resin endless toothed belt 18 instead of a metal chain. A toothed pulley 22 around which the endless toothed belt is wound is also made of resin. A rail 64 is disposed adjacent to a horizontal path of the belt, and a roller 46 attached to the belt is adapted to roll on the rail. At least two induction motors are provided for driving the endless toothed belt. The induction motors are supplied with electric power from a single inverter 35. At least a pulley is provided with a detecting unit 80. The detecting unit 80 detects a state in which teeth of the endless toothed belt climb onto that of the pulley, thereby predicting breakage of the belt. Thus, it is possible to prevent contamination of dough in a proofer.
    Type: Grant
    Filed: February 13, 2008
    Date of Patent: September 7, 2010
    Assignee: Oshikiri Machinery Ltd.
    Inventors: Kazuhide Fujita, Masayuki Koma, Koji Koike, Satoshi Goto
  • Publication number: 20100090344
    Abstract: A semiconductor device includes an insulating film formed on a semiconductor substrate, a contact wiring formed in the insulating film, a protective film formed on the contact wiring and the insulating film, an opening portion formed in the protective film, the contact wiring being exposed through the opening portion, and an electrode pad formed in the opening portion, the electrode pad being electrically connected to the contact wiring. A region where the contact wiring is not provided is present below the opening portion.
    Type: Application
    Filed: August 12, 2009
    Publication date: April 15, 2010
    Inventors: Yukitoshi Ota, Hiroshige Hirano, Yutaka Itou, Koji Koike
  • Publication number: 20090200677
    Abstract: A semiconductor device includes at least three or more wiring layers stacked in an interlayer insulating film on a semiconductor substrate, a seal ring provided at the outer periphery of a chip region of the semiconductor substrate and a chip strength reinforcement provided in part of the chip region near the seal ring. The chip strength reinforcement is made of a plurality of dummy wiring structures and each of the plurality of dummy wiring structures is formed to extend across and within two or more of the wiring layers including one or none of the bottommost wiring layer and the topmost wiring layer using a via portion.
    Type: Application
    Filed: April 27, 2009
    Publication date: August 13, 2009
    Applicant: PANASONIC CORPORATION
    Inventors: Koji TAKEMURA, Hiroshige Hirano, Yutaka Itoh, Hikari Sano, Masao Takahashi, Koji Koike
  • Patent number: 7538433
    Abstract: A semiconductor device includes at least three or more wiring layers stacked in an interlayer insulating film on a semiconductor substrate, a seal ring provided at the outer periphery of a chip region of the semiconductor substrate and a chip strength reinforcement provided in part of the chip region near the seal ring. The chip strength reinforcement is made of a plurality of dummy wiring structures and each of the plurality of dummy wiring structures is formed to extend across and within two or more of the wiring layers including one or none of the bottommost wiring layer and the topmost wiring layer using a via portion.
    Type: Grant
    Filed: June 15, 2006
    Date of Patent: May 26, 2009
    Assignee: Panasonic Corporation
    Inventors: Koji Takemura, Hiroshige Hirano, Yutaka Itoh, Hikari Sano, Masao Takahashi, Koji Koike
  • Patent number: 7521801
    Abstract: A Ti barrier film and a TiN barrier film are formed between a top-level pad made of copper or an alloy film mainly composed of copper and an Al pad. The Ti barrier film is formed to have a greater thickness than the TiN barrier film.
    Type: Grant
    Filed: October 23, 2006
    Date of Patent: April 21, 2009
    Assignee: Panasonic Corporation
    Inventors: Koji Takemura, Hiroshige Hirano, Yutaka Itoh, Koji Koike
  • Publication number: 20090051035
    Abstract: The semiconductor integrated circuit includes: a first wiring layer including a plurality of first interconnects formed to run in a first direction; a second wiring layer formed above the first wiring layer, the second wiring layer including a plurality of second interconnects formed to run in a second direction vertical to the first direction; and a third wiring layer formed above the second wiring layer, the third wiring layer including a plurality of third interconnects formed to run in the same direction as the second direction.
    Type: Application
    Filed: August 19, 2008
    Publication date: February 26, 2009
    Inventors: Hiroshige HIRANO, Koji TAKEMURA, Koji KOIKE
  • Publication number: 20080258266
    Abstract: A semiconductor device includes: an interlayer insulating film formed on a substrate; a wiring formed in the interlayer insulating film in a chip region of the substrate; a seal ring formed in the interlayer insulating film in a periphery of the chip region and continuously surrounding the chip region; and a first protective film formed on the interlayer insulating film having the wiring and the seal ring formed therein. A first opening is formed in the first protective film in a region located outside the seal ring when viewed from the chip region, and the interlayer insulating film is exposed in the first opening.
    Type: Application
    Filed: February 12, 2008
    Publication date: October 23, 2008
    Inventors: Koji TAKEMURA, Hiroshige HIRANO, Yutaka ITOH, Hikari SANO, Koji KOIKE
  • Publication number: 20080199286
    Abstract: An endless dough conveyor 16 is provided with a resin endless toothed belt 18 instead of a metal chain. A toothed pulley 22 around which the endless toothed belt is wound is also made of resin. A rail 64 is disposed adjacent to a horizontal path of the belt, and a roller 46 attached to the belt is adapted to roll on the rail. At least two induction motors are provided for driving the endless toothed belt. The induction motors are supplied with electric power from a single inverter 35. At least a pulley is provided with a detecting unit 80. The detecting unit 80 detects a state in which teeth of the endless toothed belt climb onto that of the pulley, thereby predicting breakage of the belt. Thus, it is possible to prevent contamination of dough in a proofer.
    Type: Application
    Filed: February 13, 2008
    Publication date: August 21, 2008
    Inventors: Kazuhide Fujita, Masayuki Koma, Koji Koike, Satoshi Goto
  • Publication number: 20070096320
    Abstract: A Ti barrier film and a TiN barrier film are formed between a top-level pad made of copper or an alloy film mainly composed of copper and an Al pad. The Ti barrier film is formed to have a greater thickness than the TiN barrier film.
    Type: Application
    Filed: October 23, 2006
    Publication date: May 3, 2007
    Inventors: Koji Takemura, Hiroshige Hirano, Yutaka Itoh, Koji Koike