Patents by Inventor Koji Koike
Koji Koike has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240120646Abstract: There is provided a metal plate antenna transmitting and receiving wireless signals conforming to a prescribed communication standard, wherein an antenna width is designed to satisfy radiation resistance achieving a prescribed standing wave ratio in a resonant mode in which a loop length of the metal plate antenna is 1.5 wavelength of a wireless signal conforming to the prescribed communication standard.Type: ApplicationFiled: September 6, 2023Publication date: April 11, 2024Applicant: KABUSHIKI KAISHA TOKAI RIKA DENKI SEISAKUSHOInventors: Koji INAFUNE, Kenichi KOGA, Tatsuya KOIKE, Satoshi MORI
-
Patent number: 8841753Abstract: A semiconductor device includes: an interlayer insulating film formed on a substrate; a wiring formed in the interlayer insulating film in a chip region of the substrate; a seal ring formed in the interlayer insulating film in a periphery of the chip region and continuously surrounding the chip region; and a first protective film formed on the interlayer insulating film having the wiring and the seal ring formed therein. A first opening is formed in the first protective film in a region located outside the seal ring when viewed from the chip region, and the interlayer insulating film is exposed in the first opening.Type: GrantFiled: March 23, 2012Date of Patent: September 23, 2014Assignee: Panasonic CorporationInventors: Koji Takemura, Hiroshige Hirano, Yutaka Itoh, Hikari Sano, Koji Koike
-
Patent number: 8810039Abstract: A semiconductor device includes: a semiconductor substrate; a first interlayer insulating film formed over the semiconductor substrate; a pad formed above the first interlayer insulating film; and a plurality of first interconnects spaced apart from each other in a portion of the first interlayer insulating film located below the pad. Below the pad, the first interconnects are formed in quadrangular plan shapes.Type: GrantFiled: December 12, 2011Date of Patent: August 19, 2014Assignee: Panasonic CorporationInventors: Koji Takemura, Hiroshige Hirano, Masao Takahashi, Hikari Sano, Yutaka Itoh, Koji Koike
-
Patent number: 8237281Abstract: A semiconductor device includes at least three or more wiring layers stacked in an interlayer insulating film on a semiconductor substrate, a seal ring provided at the outer periphery of a chip region of the semiconductor substrate and a chip strength reinforcement provided in part of the chip region near the seal ring. The chip strength reinforcement is made of a plurality of dummy wiring structures and each of the plurality of dummy wiring structures is formed to extend across and within two or more of the wiring layers including one or none of the bottommost wiring layer and the topmost wiring layer using a via portion.Type: GrantFiled: January 4, 2011Date of Patent: August 7, 2012Assignee: Panasonic CorporationInventors: Koji Takemura, Hiroshige Hirano, Yutaka Itoh, Hikari Sano, Masao Takahashi, Koji Koike
-
Publication number: 20120181670Abstract: A semiconductor device includes: an interlayer insulating film formed on a substrate; a wiring formed in the interlayer insulating film in a chip region of the substrate; a seal ring formed in the interlayer insulating film in a periphery of the chip region and continuously surrounding the chip region; and a first protective film formed on the interlayer insulating film having the wiring and the seal ring formed therein. A first opening is formed in the first protective film in a region located outside the seal ring when viewed from the chip region, and the interlayer insulating film is exposed in the first opening.Type: ApplicationFiled: March 23, 2012Publication date: July 19, 2012Applicant: Panasonic CorporationInventors: Koji TAKEMURA, Hiroshige Hirano, Yutaka Itoh, Hikari Sano, Koji Koike
-
Patent number: 8164163Abstract: A semiconductor device includes: an interlayer insulating film formed on a substrate; a wiring formed in the interlayer insulating film in a chip region of the substrate; a seal ring formed in the interlayer insulating film in a periphery of the chip region and continuously surrounding the chip region; and a first protective film formed on the interlayer insulating film having the wiring and the seal ring formed therein. A first opening is formed in the first protective film in a region located outside the seal ring when viewed from the chip region, and the interlayer insulating film is exposed in the first opening.Type: GrantFiled: February 12, 2008Date of Patent: April 24, 2012Assignee: Panasonic CorporationInventors: Koji Takemura, Hiroshige Hirano, Yutaka Itoh, Hikari Sano, Koji Koike
-
Publication number: 20120080780Abstract: A semiconductor device includes: a semiconductor substrate; a first interlayer insulating film formed over the semiconductor substrate; a pad formed above the first interlayer insulating film; and a plurality of first interconnects spaced apart from each other in a portion of the first interlayer insulating film located below the pad. Below the pad, the first interconnects are formed in quadrangular plan shapes.Type: ApplicationFiled: December 12, 2011Publication date: April 5, 2012Applicant: Panasonic CorporationInventors: Koji TAKEMURA, Hiroshige Hirano, Masao Takahashi, Hikari Sano, Yutaka Itoh, Koji Koike
-
Patent number: 8102056Abstract: A semiconductor device includes: a semiconductor substrate; a first interlayer insulating film formed over the semiconductor substrate; a pad formed above the first interlayer insulating film; and a plurality of first interconnects spaced apart from each other in a portion of the first interlayer insulating film located below the pad. Below the pad, the first interconnects are formed in quadrangular plan shapes.Type: GrantFiled: August 29, 2006Date of Patent: January 24, 2012Assignee: Panasonic CorporationInventors: Koji Takemura, Hiroshige Hirano, Masao Takahashi, Hikari Sano, Yutaka Itoh, Koji Koike
-
Patent number: 8044482Abstract: A semiconductor device includes an insulating film formed on a semiconductor substrate, a contact wiring formed in the insulating film, a protective film formed on the contact wiring and the insulating film, an opening portion formed in the protective film, the contact wiring being exposed through the opening portion, and an electrode pad formed in the opening portion, the electrode pad being electrically connected to the contact wiring. A region where the contact wiring is not provided is present below the opening portion.Type: GrantFiled: August 12, 2009Date of Patent: October 25, 2011Assignee: Panasonic CorporationInventors: Yukitoshi Ota, Hiroshige Hirano, Yutaka Itou, Koji Koike
-
Publication number: 20110095430Abstract: A semiconductor device includes at least three or more wiring layers stacked in an interlayer insulating film on a semiconductor substrate, a seal ring provided at the outer periphery of a chip region of the semiconductor substrate and a chip strength reinforcement provided in part of the chip region near the seal ring. The chip strength reinforcement is made of a plurality of dummy wiring structures and each of the plurality of dummy wiring structures is formed to extend across and within two or more of the wiring layers including one or none of the bottommost wiring layer and the topmost wiring layer using a via portion.Type: ApplicationFiled: January 4, 2011Publication date: April 28, 2011Applicant: PANASONIC CORPORATIONInventors: Koji TAKEMURA, Hiroshige Hirano, Yutaka Itoh, Hikari Sano, Masao Takahashi, Koji Koike
-
Patent number: 7888801Abstract: A semiconductor device includes at least three or more wiring layers stacked in an interlayer insulating film on a semiconductor substrate, a seal ring provided at the outer periphery of a chip region of the semiconductor substrate and a chip strength reinforcement provided in part of the chip region near the seal ring. The chip strength reinforcement is made of a plurality of dummy wiring structures and each of the plurality of dummy wiring structures is formed to extend across and within two or more of the wiring layers including one or none of the bottommost wiring layer and the topmost wiring layer using a via portion.Type: GrantFiled: April 27, 2009Date of Patent: February 15, 2011Assignee: Panasonic CorporationInventors: Koji Takemura, Hiroshige Hirano, Yutaka Itoh, Hikari Sano, Masao Takahashi, Koji Koike
-
Patent number: 7789222Abstract: An endless dough conveyor 16 is provided with a resin endless toothed belt 18 instead of a metal chain. A toothed pulley 22 around which the endless toothed belt is wound is also made of resin. A rail 64 is disposed adjacent to a horizontal path of the belt, and a roller 46 attached to the belt is adapted to roll on the rail. At least two induction motors are provided for driving the endless toothed belt. The induction motors are supplied with electric power from a single inverter 35. At least a pulley is provided with a detecting unit 80. The detecting unit 80 detects a state in which teeth of the endless toothed belt climb onto that of the pulley, thereby predicting breakage of the belt. Thus, it is possible to prevent contamination of dough in a proofer.Type: GrantFiled: February 13, 2008Date of Patent: September 7, 2010Assignee: Oshikiri Machinery Ltd.Inventors: Kazuhide Fujita, Masayuki Koma, Koji Koike, Satoshi Goto
-
Publication number: 20100090344Abstract: A semiconductor device includes an insulating film formed on a semiconductor substrate, a contact wiring formed in the insulating film, a protective film formed on the contact wiring and the insulating film, an opening portion formed in the protective film, the contact wiring being exposed through the opening portion, and an electrode pad formed in the opening portion, the electrode pad being electrically connected to the contact wiring. A region where the contact wiring is not provided is present below the opening portion.Type: ApplicationFiled: August 12, 2009Publication date: April 15, 2010Inventors: Yukitoshi Ota, Hiroshige Hirano, Yutaka Itou, Koji Koike
-
Publication number: 20090200677Abstract: A semiconductor device includes at least three or more wiring layers stacked in an interlayer insulating film on a semiconductor substrate, a seal ring provided at the outer periphery of a chip region of the semiconductor substrate and a chip strength reinforcement provided in part of the chip region near the seal ring. The chip strength reinforcement is made of a plurality of dummy wiring structures and each of the plurality of dummy wiring structures is formed to extend across and within two or more of the wiring layers including one or none of the bottommost wiring layer and the topmost wiring layer using a via portion.Type: ApplicationFiled: April 27, 2009Publication date: August 13, 2009Applicant: PANASONIC CORPORATIONInventors: Koji TAKEMURA, Hiroshige Hirano, Yutaka Itoh, Hikari Sano, Masao Takahashi, Koji Koike
-
Patent number: 7538433Abstract: A semiconductor device includes at least three or more wiring layers stacked in an interlayer insulating film on a semiconductor substrate, a seal ring provided at the outer periphery of a chip region of the semiconductor substrate and a chip strength reinforcement provided in part of the chip region near the seal ring. The chip strength reinforcement is made of a plurality of dummy wiring structures and each of the plurality of dummy wiring structures is formed to extend across and within two or more of the wiring layers including one or none of the bottommost wiring layer and the topmost wiring layer using a via portion.Type: GrantFiled: June 15, 2006Date of Patent: May 26, 2009Assignee: Panasonic CorporationInventors: Koji Takemura, Hiroshige Hirano, Yutaka Itoh, Hikari Sano, Masao Takahashi, Koji Koike
-
Patent number: 7521801Abstract: A Ti barrier film and a TiN barrier film are formed between a top-level pad made of copper or an alloy film mainly composed of copper and an Al pad. The Ti barrier film is formed to have a greater thickness than the TiN barrier film.Type: GrantFiled: October 23, 2006Date of Patent: April 21, 2009Assignee: Panasonic CorporationInventors: Koji Takemura, Hiroshige Hirano, Yutaka Itoh, Koji Koike
-
Publication number: 20090051035Abstract: The semiconductor integrated circuit includes: a first wiring layer including a plurality of first interconnects formed to run in a first direction; a second wiring layer formed above the first wiring layer, the second wiring layer including a plurality of second interconnects formed to run in a second direction vertical to the first direction; and a third wiring layer formed above the second wiring layer, the third wiring layer including a plurality of third interconnects formed to run in the same direction as the second direction.Type: ApplicationFiled: August 19, 2008Publication date: February 26, 2009Inventors: Hiroshige HIRANO, Koji TAKEMURA, Koji KOIKE
-
Publication number: 20080258266Abstract: A semiconductor device includes: an interlayer insulating film formed on a substrate; a wiring formed in the interlayer insulating film in a chip region of the substrate; a seal ring formed in the interlayer insulating film in a periphery of the chip region and continuously surrounding the chip region; and a first protective film formed on the interlayer insulating film having the wiring and the seal ring formed therein. A first opening is formed in the first protective film in a region located outside the seal ring when viewed from the chip region, and the interlayer insulating film is exposed in the first opening.Type: ApplicationFiled: February 12, 2008Publication date: October 23, 2008Inventors: Koji TAKEMURA, Hiroshige HIRANO, Yutaka ITOH, Hikari SANO, Koji KOIKE
-
Publication number: 20080199286Abstract: An endless dough conveyor 16 is provided with a resin endless toothed belt 18 instead of a metal chain. A toothed pulley 22 around which the endless toothed belt is wound is also made of resin. A rail 64 is disposed adjacent to a horizontal path of the belt, and a roller 46 attached to the belt is adapted to roll on the rail. At least two induction motors are provided for driving the endless toothed belt. The induction motors are supplied with electric power from a single inverter 35. At least a pulley is provided with a detecting unit 80. The detecting unit 80 detects a state in which teeth of the endless toothed belt climb onto that of the pulley, thereby predicting breakage of the belt. Thus, it is possible to prevent contamination of dough in a proofer.Type: ApplicationFiled: February 13, 2008Publication date: August 21, 2008Inventors: Kazuhide Fujita, Masayuki Koma, Koji Koike, Satoshi Goto
-
Publication number: 20070096320Abstract: A Ti barrier film and a TiN barrier film are formed between a top-level pad made of copper or an alloy film mainly composed of copper and an Al pad. The Ti barrier film is formed to have a greater thickness than the TiN barrier film.Type: ApplicationFiled: October 23, 2006Publication date: May 3, 2007Inventors: Koji Takemura, Hiroshige Hirano, Yutaka Itoh, Koji Koike