Patents by Inventor Koji Muranaka

Koji Muranaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8642406
    Abstract: An object of the present invention is to increase adhesiveness between thin films, particularly a high molecular film formed on an insulating surface, and the present invention provides a semiconductor device with high reliability and a method for manufacturing the semiconductor device with high yield. A semiconductor device of the present invention comprises a laminate structure formed in close contact with an organic insulating film on a hydrophobic surface of an inorganic insulating film including silicon and nitrogen. A film having the hydrophobic surface is an insulating film having a contact angle of water of equal to or more than 30°, preferably of equal to or more than 40°.
    Type: Grant
    Filed: September 9, 2011
    Date of Patent: February 4, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Koji Muranaka
  • Patent number: 8278204
    Abstract: It is required that a line width of a wiring is prevented from being wider to be miniaturized when the wiring or the like is formed by a dropping method typified by an ink-jetting method. The invention provides a method for narrowing (miniaturizing) a line width according to a method different from a conventional method. One feature of the invention is that a plasma treatment is performed before forming a wiring or the like by a dropping method typified by an ink-jetting method. As the result of the plasma treatment, a surface for forming a conductive film is modified to be liquid-repellent. Consequently, a wiring or the like formed by a dropping method can be miniaturized.
    Type: Grant
    Filed: January 24, 2011
    Date of Patent: October 2, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shinji Maekawa, Koji Muranaka
  • Publication number: 20120064729
    Abstract: An object of the present invention is to increase adhesiveness between thin films, particularly a high molecular film formed on an insulating surface, and the present invention provides a semiconductor device with high reliability and a method for manufacturing the semiconductor device with high yield. A semiconductor device of the present invention comprises a laminate structure formed in close contact with an organic insulating film on a hydrophobic surface of an inorganic insulating film including silicon and nitrogen. A film having the hydrophobic surface is an insulating film having a contact angle of water of equal to or more than 30°, preferably of equal to or more than 40°.
    Type: Application
    Filed: September 9, 2011
    Publication date: March 15, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Koji MURANAKA
  • Patent number: 8017455
    Abstract: An object of the present invention is to increase adhesiveness between thin films, particularly a high molecular film formed on an insulating surface, and the present invention provides a semiconductor device with high reliability and a method for manufacturing the semiconductor device with high yield. A semiconductor device of the present invention comprises a laminate structure formed in close contact with an organic insulating film on a hydrophobic surface of an inorganic insulating film including silicon and nitrogen. A film having the hydrophobic surface is an insulating film having a contact angle of water of equal to or more than 30°, preferably of equal to or more than 40°.
    Type: Grant
    Filed: March 16, 2006
    Date of Patent: September 13, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Koji Muranaka
  • Publication number: 20110177689
    Abstract: It is required that a line width of a wiring is prevented from being wider to be miniaturized when the wiring or the like is formed by a dropping method typified by an ink-jetting method. The invention provides a method for narrowing (miniaturizing) a line width according to a method different from a conventional method. One feature of the invention is that a plasma treatment is performed before forming a wiring or the like by a dropping method typified by an ink-jetting method. As the result of the plasma treatment, a surface for forming a conductive film is modified to be liquid-repellent. Consequently, a wiring or the like formed by a dropping method can be miniaturized.
    Type: Application
    Filed: January 24, 2011
    Publication date: July 21, 2011
    Inventors: Shinji Maekawa, Koji Muranaka
  • Patent number: 7968461
    Abstract: It is required that a line width of a wiring is prevented from being wider to be miniaturized when the wiring or the like is formed by a dropping method typified by an ink-jetting method. Therefore, the invention provides a method for narrowing (miniaturizing) the line width according to a method different from a conventional method. A region to be liquid-repellent is formed and further, a region to be lyophilic is formed selectively in the region to be liquid-repellent in a surface for forming a pattern, before forming a desired pattern. After that, a pattern for a wiring or the like is formed in the lyophilic region by a dropping method typified by an ink-jetting method for dropping a composition including a conductive material for the wiring or the like.
    Type: Grant
    Filed: October 25, 2004
    Date of Patent: June 28, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shinji Maekawa, Shunpei Yamazaki, Yuko Tachimura, Koji Muranaka
  • Patent number: 7875542
    Abstract: It is required that a line width of a wiring is prevented from being wider to be miniaturized when the wiring or the like is formed by a dropping method typified by an ink-jetting method. The invention provides a method for narrowing (miniaturizing) a line width according to a method different from a conventional method. One feature of the invention is that a plasma treatment is performed before forming a wiring or the like by a dropping method typified by an ink-jetting method. As the result of the plasma treatment, a surface for forming a conductive film is modified to be liquid-repellent. Consequently, a wiring or the like formed by a dropping method can be miniaturized.
    Type: Grant
    Filed: May 17, 2007
    Date of Patent: January 25, 2011
    Assignee: Semiconductor Energy laboratory Co., Ltd.
    Inventors: Shinji Maekawa, Koji Muranaka
  • Patent number: 7449408
    Abstract: It is an object of the present invention to provide a method for manufacturing a semiconductor device in which a desired region can be etched by evenly applying a solution including a resist and a method for manufacturing a semiconductor device having a laminated structure by forming an interlayer insulating layer with an organic resin.
    Type: Grant
    Filed: June 8, 2004
    Date of Patent: November 11, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Koji Muranaka, Ryoji Nomura, Takeshi Shichi, Tatsuya Arao, Masahiro Katayama
  • Patent number: 7354808
    Abstract: An object of the invention is to provide a resist composition which is possible to form a film by using a drawing means and which functions as a protective film used at the time of etching, adding impurities, or the like. In addition, an object is also to provide a manufacturing step of a semiconductor device in which a substance with high safety and that is easily treated can be used as a peeling solution, and which pays attention to an environment. A resist composition of the invention contains water-soluble homopolymer, water, or a solvent that has compatibility with water and can dissolve the water-soluble homopolymer. In addition, a method for manufacturing the semiconductor device of the invention has a step of removing the protective film formed by discharging the resist composition of the invention by using a drawing means with water after using it.
    Type: Grant
    Filed: August 11, 2004
    Date of Patent: April 8, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Koji Muranaka, Ryoji Nomura, Keitaro Imai, Shinji Maekawa
  • Publication number: 20070218674
    Abstract: It is required that a line width of a wiring is prevented from being wider to be miniaturized when the wiring or the like is formed by a dropping method typified by an ink-jetting method. The invention provides a method for narrowing (miniaturizing) a line width according to a method different from a conventional method. One feature of the invention is that a plasma treatment is performed before forming a wiring or the like by a dropping method typified by an ink-jetting method. As the result of the plasma treatment, a surface for forming a conductive film is modified to be liquid-repellent. Consequently, a wiring or the like formed by a dropping method can be miniaturized.
    Type: Application
    Filed: May 17, 2007
    Publication date: September 20, 2007
    Inventors: Shinji Maekawa, Koji Muranaka
  • Publication number: 20070164280
    Abstract: The present invention provides a thin film transistor that can be manufactured at lower cost and at higher yield by simplifying a manufacturing process, a manufacturing method thereof, and a manufacturing method of a display device using the thin film transistor. According to this invention, a pattern used in a pattering process is formed by using a droplet discharging method. The pattern is formed by selectively discharging a composition comprising an organic resin. By using the pattern, an electrically conductive material, an insulator or semiconductor constituting a semiconductor element, are patterned into a desired shape by a simple process.
    Type: Application
    Filed: August 25, 2004
    Publication date: July 19, 2007
    Inventors: Shinji Maekawa, Osamu Nakamura, Koji Muranaka
  • Patent number: 7226819
    Abstract: It is required that a line width of a wiring is prevented from being wider to be miniaturized when the wiring or the like is formed by a dropping method typified by an ink-jetting method. The invention provides a method for narrowing (miniaturizing) a line width according to a method different from a conventional method. One feature of the invention is that a plasma treatment is performed before forming a wiring or the like by a dropping method typified by an ink-jetting method. As the result of the plasma treatment, a surface for forming a conductive film is modified to be liquid-repellent. Consequently, a wiring or the like formed by a dropping method can be miniaturized.
    Type: Grant
    Filed: October 21, 2004
    Date of Patent: June 5, 2007
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shinji Maekawa, Koji Muranaka
  • Publication number: 20070019032
    Abstract: It is required that a line width of a wiring is prevented from being wider to be miniaturized when the wiring or the like is formed by a dropping method typified by an ink-jetting method. Therefore, the invention provides a method for narrowing (miniaturizing) the line width according to a method different from a conventional method. A region to be liquid-repellent is formed and further, a region to be lyophilic is formed selectively in the region to be liquid-repellent in a surface for forming a pattern, before forming a desired pattern. After that, a pattern for a wiring or the like is formed in the lyophilic region by a dropping method typified by an ink-jetting method for dropping a composition including a conductive material for the wiring or the like.
    Type: Application
    Filed: October 25, 2004
    Publication date: January 25, 2007
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shinji Maekawa, Shunpei Yamazaki, Yuko Tachimura, Koji Muranaka
  • Patent number: 7160820
    Abstract: There is provided a process for preparing a composite material of an oxide crystal film and a substrate by forming a Y123 type oxide crystal film from a solution phase on a substrate using a liquid phase method, wherein problems such as cracking of the oxide crystal film, separation of the oxide crystal film from the substrate, and development of a reaction layer between the substrate and the solution can be minimized. The solvent for forming the solution phase uses either a BaO—CuO—BaF2 system or a BaO—CuO—Ag—BaF2 system, and when the substrate with a seed crystal film bonded to the surface is brought in contact with the solution to form (grow) the oxide crystal film on the substrate, the temperature of the solution is controlled to a temperature of no more than 850° C.
    Type: Grant
    Filed: May 15, 2002
    Date of Patent: January 9, 2007
    Assignees: International Superconductivity Technology Center, the Juridical Foundation, Fujikura Ltd.
    Inventors: Toshihiro Suga, Yasuji Yamada, Toshihiko Maeda, Seok Beom Kim, Haruhiko Kurosaki, Yutaka Yamada, Izumi Hirabayashi, Yasuhiro Iijima, Tomonori Watanabe, Hisashi Yoshino, Koji Muranaka
  • Publication number: 20060160357
    Abstract: An object of the present invention is to increase adhesiveness between thin films, particularly a high molecular film formed on an insulating surface, and the present invention provides a semiconductor device with high reliability and a method for manufacturing the semiconductor device with high yield. A semiconductor device of the present invention comprises a laminate structure formed in close contact with an organic insulating film on a hydrophobic surface of an inorganic insulating film including silicon and nitrogen. A film having the hydrophobic surface is an insulating film having a contact angle of water of equal to or more than 30°, preferably of equal to or more than 40°.
    Type: Application
    Filed: March 16, 2006
    Publication date: July 20, 2006
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Koji Muranaka
  • Patent number: 7038303
    Abstract: An object of the present invention is to increase adhesiveness between thin films, particularly a high molecular film formed on an insulating surface, and the present invention provides a semiconductor device with high reliability and a method for manufacturing the semiconductor device with high yield. A semiconductor device of the present invention comprises a laminate structure formed in close contact with an organic insulating film on a hydrophobic surface of an inorganic insulating film including silicon and nitrogen. A film having the hydrophobic surface is an insulating film having a contact angle of water of equal to or more than 30°, preferably of equal to or more than 40°.
    Type: Grant
    Filed: March 25, 2004
    Date of Patent: May 2, 2006
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Koji Muranaka
  • Publication number: 20050164520
    Abstract: It is an object of the present invention to provide a method for manufacturing a semiconductor device in which a desired region can be etched by evenly applying a solution including a resist and a method for manufacturing a semiconductor device having a laminated structure by forming an interlayer insulating layer with an organic resin.
    Type: Application
    Filed: June 8, 2004
    Publication date: July 28, 2005
    Inventors: Koji Muranaka, Ryoji Nomura, Takeshi Shichi, Tatsuya Arao, Masahiro Katayama
  • Publication number: 20050112906
    Abstract: It is required that a line width of a wiring is prevented from being wider to be miniaturized when the wiring or the like is formed by a dropping method typified by an ink-jetting method. The invention provides a method for narrowing (miniaturizing) a line width according to a method different from a conventional method. One feature of the invention is that a plasma treatment is performed before forming a wiring or the like by a dropping method typified by an ink-jetting method. As the result of the plasma treatment, a surface for forming a conductive film is modified to be liquid-repellent. Consequently, a wiring or the like formed by a dropping method can be miniaturized.
    Type: Application
    Filed: October 21, 2004
    Publication date: May 26, 2005
    Inventors: Shinji Maekawa, Koji Muranaka
  • Publication number: 20050048289
    Abstract: An object of the invention is to provide a resist composition which is possible to form a film by using a drawing means and which functions as a protective film used at the time of etching, adding impurities, or the like. In addition, an object is also to provide a manufacturing step of a semiconductor device in which a substance with high safety and that is easily treated can be used as a peeling solution, and which pays attention to an environment. A resist composition of the invention contains water-soluble homopolymer, water, or a solvent that has compatibility with water and can dissolve the water-soluble homopolymer. In addition, a method for manufacturing the semiconductor device of the invention has a step of removing the protective film formed by discharging the resist composition of the invention by using a drawing means with water after using it.
    Type: Application
    Filed: August 11, 2004
    Publication date: March 3, 2005
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Koji Muranaka, Ryoji Nomura, Keitaro Imai, Shinji Maekawa
  • Publication number: 20050016633
    Abstract: The method of manufacturing soft magnetic articles comprises a step of preparing a melt solution containing soft magnetic materials and a step of forming soft magnetic particles from the melt solution in a magnetic field by an atomization rapid solidification method.
    Type: Application
    Filed: July 20, 2004
    Publication date: January 27, 2005
    Inventors: Hirokazu Kugai, Haruhisa Toyoda, Naoto Igarashi, Kazuhiro Hirose, Takao Nishioka, Akihiko Ikegaya, Ryosuke Hata, Hitoshi Oyama, Kenichi Sato, Kazuhiko Hayashi, Masayuki Hirose, koji Muranaka