Patents by Inventor Koji Nii

Koji Nii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10770160
    Abstract: Architecture, design, structure, layout, and method of forming a Programmable Resistive Device (PRD) memory in standard cell library are disclosed. The PRD memory has a plurality of PRD cells. At least one of the PRD cells can have a PRD element coupled to a first supply voltage line and coupled to a second supply voltage line through a program selector. The PRD cells reside in a standard cell library and following most of the standard cell design and layout guidelines.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: September 8, 2020
    Assignees: Attopsemi Technology Co., LTD, Renesas Electronics Corporation
    Inventors: Shine C. Chung, Koji Nii
  • Patent number: 10734063
    Abstract: A semiconductor device includes: a first cell; a second cell; a first match line and a second match line; a first search line pair, first data being transmitted through the first search line pair; a second search line pair, second data being transmitted through the second search line pair; a first logical operation cell connected to the first search line pair and the first match line, and configured to drive the first match line based on a result of comparison between information held by the first and second cells and the first data; and a second logical operation cell connected to the second search line pair and the second match line, and configured to drive the second match line based on a result of comparison between information held by the first and second cells and the second data.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: August 4, 2020
    Assignee: Renesas Electronics Corporation
    Inventor: Koji Nii
  • Patent number: 10706917
    Abstract: Provided is a semiconductor memory device having a low power consumption write assist circuit. The semiconductor memory device includes multiple word lines, multiple bit line pairs, multiple memory cells, multiple auxiliary line pairs, a write driver circuit, a write assist circuit, and a select circuit. The memory cells are coupled to the word lines and the bit line pairs in such a manner that one memory cell is coupled to one word line and one bit line pair. The auxiliary line pairs run parallel to the bit line pairs in such a manner that one auxiliary line pair runs parallel to one bit line pair. The select circuit couples, to the write driver circuit, one bit line pair selected from the bit line pairs in accordance with a select signal, and couples, to the write assist circuit, an associated auxiliary line pair running parallel to the selected bit line pair.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: July 7, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Koji Nii, Yuichiro Ishii, Yohei Sawada, Makoto Yabuuchi
  • Publication number: 20200140462
    Abstract: Provided is a compound represented by the following formula, or a salt thereof: [wherein each symbol is as defined herein.].
    Type: Application
    Filed: October 25, 2019
    Publication date: May 7, 2020
    Applicant: TAKEDA PHARMACEUTICAL COMPANY LIMITED
    Inventors: Youichi KAWAKITA, Takuto KOJIMA, Noriyuki NII, Yoshiteru ITO, Nobuki SAKAUCHI, Hiroshi BANNO, Xin LIU, Koji ONO, Keisuke IMAMURA, Shinichi IMAMURA
  • Patent number: 10644009
    Abstract: To provide a semiconductor memory device fast in address access time. The semiconductor memory device includes a plurality of memory cells, and a word line coupled to the memory cells. The word line is extended in a first direction. Each of the memory cells includes gate electrodes extended in a second direction intersecting with the first direction.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: May 5, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Koji Nii, Makoto Yabuuchi
  • Patent number: 10577382
    Abstract: Provided is a compound represented by the following formula, or a salt thereof: [wherein each symbol is as defined herein].
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: March 3, 2020
    Assignee: TAKEDA PHARMACEUTICAL COMPANY LIMITED
    Inventors: Youichi Kawakita, Takuto Kojima, Noriyuki Nii, Yoshiteru Ito, Nobuki Sakauchi, Hiroshi Banno, Xin Liu, Koji Ono, Keisuke Imamura, Shinichi Imamura
  • Patent number: 10580490
    Abstract: A semiconductor device is provided where high-speed search operation can be performed. The semiconductor device includes a plurality of search memory cells arranged in a matrix form a plurality of search line pairs which are respectively provided corresponding to memory cell columns and which respectively transmit a plurality of search data to be compared with data stored in the search memory cells, a plurality of search drivers which are respectively arranged at corresponding to one end sides of the search line pairs and which drive the search line pairs according to the search data, and a plurality of assist circuits which are respectively provided corresponding to the other end sides of the search line pairs and which assist driving corresponding search line pairs according to the search data.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: March 3, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Makoto Yabuuchi, Koji Nii
  • Patent number: 10510761
    Abstract: In a region just below an access gate electrode in an SRAM memory cell, a second halo region is formed adjacent to a source-drain region and a first halo region is formed adjacent to a first source-drain region. In a region just below a drive gate electrode, a third halo region is formed adjacent to the third source-drain region and a fourth halo region is formed adjacent to a fourth source-drain region. The second halo region is set to have an impurity concentration higher than the impurity concentration of the first halo region. The third halo region is set to have an impurity concentration higher than the impurity concentration of the fourth halo region. The impurity concentration of the first halo region and the impurity concentration of the fourth halo region are different from each other.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: December 17, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Kengo Masuda
  • Publication number: 20190329666
    Abstract: A communication device comprises a connector to which a communication line is to be connected for sending and receiving a control signal concerning charge control between a transportation apparatus and a charging apparatus, a modem outputting a modulated signal obtained by modulating information to be sent and demodulating the modulated signal input, and a first internal communication line and a second internal communication line each being connected to the connector and the modem, the first internal communication line and the second internal communication line respectively being for sending the modulated signal and being for receiving the modulated signal, and sends and receives the modulated signal by superposing the modulated signal on the control signal.
    Type: Application
    Filed: June 2, 2017
    Publication date: October 31, 2019
    Inventors: Yuichi KODAMA, Ryo OKADA, Takeshi HAGIHARA, Kazuhiko NII, Koji SAOTOME, Shuta FUKUDA
  • Publication number: 20190259443
    Abstract: A semiconductor device includes: a first cell; a second cell; a first match line and a second match line; a first search line pair, first data being transmitted through the first search line pair; a second search line pair, second data being transmitted through the second search line pair; a first logical operation cell connected to the first search line pair and the first match line, and configured to drive the first match line based on a result of comparison between information held by the first and second cells and the first data; and a second logical operation cell connected to the second search line pair and the second match line, and configured to drive the second match line based on a result of comparison between information held by the first and second cells and the second data.
    Type: Application
    Filed: February 27, 2019
    Publication date: August 22, 2019
    Applicant: Renesas Electronics Corporation
    Inventor: Koji NII
  • Patent number: 10381056
    Abstract: A dual port static random access memory (DPSRAM) cell includes a first power line, a first bit line and a second bit line. The first power line is disposed between a first word line and a second word line. The first bit line is disposed between the first word line and the first power line. The second bit line is disposed between the second word line and the first power line.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: August 13, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tien-Yu Lu, Chun-Hsien Huang, Ching-Cheng Lung, Yu-Tse Kuo, Shou-Sian Chen, Koji Nii, Yuichiro Ishii
  • Publication number: 20190206459
    Abstract: A dual port static random access memory (DPSRAM) cell includes a first power line, a first bit line and a second bit line. The first power line is disposed between a first word line and a second word line. The first bit line is disposed between the first word line and the first power line. The second bit line is disposed between the second word line and the first power line.
    Type: Application
    Filed: May 29, 2018
    Publication date: July 4, 2019
    Inventors: Tien-Yu Lu, Chun-Hsien Huang, Ching-Cheng Lung, Yu-Tse Kuo, Shou-Sian Chen, Koji Nii, Yuichiro Ishii
  • Publication number: 20190198107
    Abstract: A semiconductor device is provided where high-speed search operation can be performed. The semiconductor device includes a plurality of search memory cells arranged in a matrix form a plurality of search line pairs which are respectively provided corresponding to memory cell columns and which respectively transmit a plurality of search data to be compared with data stored in the search memory cells, a plurality of search drivers which are respectively arranged at corresponding to one end sides of the search line pairs and which drive the search line pairs according to the search data, and a plurality of assist circuits which are respectively provided corresponding to the other end sides of the search line pairs and which assist driving corresponding search line pairs according to the search data.
    Type: Application
    Filed: November 15, 2018
    Publication date: June 27, 2019
    Inventors: Makoto YABUUCHI, Koji NII
  • Publication number: 20190198507
    Abstract: To provide a semiconductor memory device fast in address access time. The semiconductor memory device includes a plurality of memory cells, and a word line coupled to the memory cells. The word line is extended in a first direction. Each of the memory cells includes gate electrodes extended in a second direction intersecting with the first direction.
    Type: Application
    Filed: November 1, 2018
    Publication date: June 27, 2019
    Inventors: Koji NII, Makoto YABUUCHI
  • Publication number: 20190189197
    Abstract: Provided is a semiconductor memory device having a low power consumption write assist circuit. The semiconductor memory device includes multiple word lines, multiple bit line pairs, multiple memory cells, multiple auxiliary line pairs, a write driver circuit, a write assist circuit, and a select circuit. The memory cells are coupled to the word lines and the bit line pairs in such a manner that one memory cell is coupled to one word line and one bit line pair. The auxiliary line pairs run parallel to the bit line pairs in such a manner that one auxiliary line pair runs parallel to one bit line pair. The select circuit couples, to the write driver circuit, one bit line pair selected from the bit line pairs in accordance with a select signal, and couples, to the write assist circuit, an associated auxiliary line pair running parallel to the selected bit line pair.
    Type: Application
    Filed: October 31, 2018
    Publication date: June 20, 2019
    Inventors: Koji NII, Yuichiro ISHII, Yohei SAWADA, Makoto YABUUCHI
  • Publication number: 20190139966
    Abstract: In a region just below an access gate electrode in an SRAM memory cell, a second halo region is formed adjacent to a source-drain region and a first halo region is formed adjacent to a first source-drain region. In a region just below a drive gate electrode, a third halo region is formed adjacent to the third source-drain region and a fourth halo region is formed adjacent to a fourth source-drain region. The second halo region is set to have an impurity concentration higher than the impurity concentration of the first halo region. The third halo region is set to have an impurity concentration higher than the impurity concentration of the fourth halo region. The impurity concentration of the first halo region and the impurity concentration of the fourth halo region are different from each other.
    Type: Application
    Filed: January 4, 2019
    Publication date: May 9, 2019
    Inventors: Koji NII, Makoto YABUUCHI, Yasumasa TSUKAMOTO, Kengo MASUDA
  • Patent number: 10262720
    Abstract: A semiconductor device includes: a first cell; a second cell; a first match line and a second match line; a first search line pair, first data being transmitted through the first search line pair; a second search line pair, second data being transmitted through the second search line pair; a first logical operation cell connected to the first search line pair and the first match line, and configured to drive the first match line based on a result of comparison between information held by the first and second cells and the first data; and a second logical operation cell connected to the second search line pair and the second match line, and configured to drive the second match line based on a result of comparison between information held by the first and second cells and the second data.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: April 16, 2019
    Assignee: Renesas Electroncis Corporation
    Inventor: Koji Nii
  • Patent number: 10262707
    Abstract: In a semiconductor memory device, static memory cells are arranged in rows and columns, word lines correspond to respective memory cell rows, and word line drivers drive correspond to word lines. Cell power supply lines correspond to respective memory cell columns and are coupled to cell power supply nodes of a memory cell in a corresponding column. Down power supply lines are arranged corresponding to respective memory cell columns, maintained at ground voltage in data reading and rendered electrically floating in data writing. Write assist elements are arranged corresponding to the cell power supply lines, and according to a write column instruction signal for stopping supply of a cell power supply voltage to the cell power supply line in a selected column, and for coupling the cell power supply line arranged corresponding to the selected column at least to the down power supply line on the corresponding column.
    Type: Grant
    Filed: May 4, 2017
    Date of Patent: April 16, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Koji Nii, Shigeki Ohbayashi, Yasumasa Tsukamoto, Makoto Yabuuchi
  • Patent number: RE47679
    Abstract: A semiconductor memory having a memory cell structure capable of reducing soft error without complicating a circuit configuration. Specifically, an inverter (I1) consists of a NMOS transistor (N1) and a PMOS transistor (P1), and an inverter (I2) consists of a NMOS transistor (N2) and a PMOS transistor (P2). The inverters (I1, I2) are subjected to cross section. The NMOS transistor (N1) is formed within a P well region (PW0), and the NMOS transistor (N2) is formed within a P well region (PW1). The P well regions (PW0, PW1) are oppositely disposed with an N well region (NW) interposed therebetween.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: October 29, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Koji Nii
  • Patent number: RE47831
    Abstract: A semiconductor memory having a memory cell structure capable of reducing soft error without complicating a circuit configuration. Specifically, an inverter (I1) consists of a NMOS transistor (N1) and a PMOS transistor (P1), and an inverter (I2) consists of a NMOS transistor (N2) and a PMOS transistor (P2). The inverters (I1, I2) are subjected to cross section. The NMOS transistor (N1) is formed within a P well region (PW0), and the NMOS transistor (N2) is formed within a P well region (PW1). The P well regions (PW0, PW1) are oppositely disposed with an N well region (NW) interposed therebetween.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: January 28, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Koji Nii