Patents by Inventor Koji Odaira

Koji Odaira has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6989587
    Abstract: There is provided a semiconductor device with enhanced reliability having a heat sink mounting a plurality of semiconductor chips, a plurality of inner leads connected electrically to the semiconductor chips, a molding body for resin molding the plurality of semiconductor chips and the plurality of inner leads, a plurality of wires for providing electrical connections between the respective electrodes of the semiconductor chips and the inner leads corresponding thereto, and wide outer leads connecting to the inner leads and exposed outside the molding body. A plurality of slits are formed in the respective portions of the outer leads located outside the molding body to extend lengthwise in directions in which the outer leads are extracted. This achieves a reduction in lead stress which is placed on the outer leads by thermal stress or the like after the mounting of a MOSFET and thereby enhances the reliability of the MOSFET.
    Type: Grant
    Filed: December 9, 2003
    Date of Patent: January 24, 2006
    Assignees: Renesas Technology Corp., Renesas Esatern Japan Semiconductor, Inc.
    Inventors: Mamoru Ito, Akira Muto, Tomio Yamada, Tsuneo Endoh, Satoru Konishi, Kazuaki Uehara, Tsutomu Ida, Koji Odaira, Hirokazu Nakajima
  • Publication number: 20040145034
    Abstract: A semiconductor device for amplification with enhanced performance is provided for use at a base station. The semiconductor device has a semiconductor chip for amplification and a transmission line substrate in the package of an amplifier used at a base station for mobile communication equipment such as a mobile phone. Stubs formed in the empty region of the transmission line substrate are connected to an output of the semiconductor chip for amplification by using bonding wires. The stubs and the bonding wires have been designed to form a resonant circuit resonating at a frequency double the fundamental frequency of an output signal from the semiconductor chip for amplification. This suppresses a doubled-frequency-wave signal of the signal outputted from the semiconductor chip for amplification and achieves an improvement in the transmission efficiency of the amplifier and a reduction in transmission distortion.
    Type: Application
    Filed: January 9, 2004
    Publication date: July 29, 2004
    Inventors: Toru Fujioka, Toshihiko Shimizu, Isao Yoshida, Mamoru Ito, Koji Odaira, Tetsuya Iida
  • Publication number: 20040113248
    Abstract: There is provided a semiconductor device with enhanced reliability having a heat sink mounting a plurality of semiconductor chips, a plurality of inner leads connected electrically to the semiconductor chips, a molding body for resin molding the plurality of semiconductor chips and the plurality of inner leads, a plurality of wires for providing electrical connections between the respective electrodes of the semiconductor chips and the inner leads corresponding thereto, and wide outer leads connecting to the inner leads and exposed outside the molding body. A plurality of slits are formed in the respective portions of the outer leads located outside the molding body to extend lengthwise in directions in which the outer leads are extracted. This achieves a reduction in lead stress which is placed on the outer leads by thermal stress or the like after the mounting of a MOSFET and thereby enhances the reliability of the MOSFET.
    Type: Application
    Filed: December 9, 2003
    Publication date: June 17, 2004
    Inventors: Mamoru Ito, Akira Muto, Tomio Yamada, Tsuneo Endoh, Satoru Konishi, Kazuaki Uehara, Tsutomu Ida, Koji Odaira, Hirokazu Nakajima