Abstract: A communication apparatus is disclosed that includes a transmission circuit configured to transmit transmission data to a communication counterpart; a reception circuit configured to receive reception data from the communication counterpart; a storage device configured as at least two buffers including a transmission buffer that stores the transmission data and a reception buffer that stores the reception data; and an address mapping unit configured to perform address mapping of the buffers including the transmission buffer and the reception buffer on the storage device, and adjust the storage capacity of the transmission buffer and the storage capacity of the reception buffer.

Abstract: A statistical-information generating unit monitors packet data output from a transaction layer that constitutes architecture of a PCI Express. The result of the monitored is feedback-controlled to a weight-information updating unit in real time, and is reflected in an arbitration table. A priority is set to the packet data corresponding to a quantity of the packet data actually transferred on a serial communication path.

Abstract: An image forming apparatus includes an image input device that reads an image to obtain image data and a printer engine that forms an image on a medium based on image data. A bus of a PCI Express standard is used to transfer data. Storage areas serving as end points of the standard and hardware resources that transmit data and receive image data to and from the storage areas are connected to an identical switch according to the PCI Express standard. Specifically, an input/output area, an image input device, and a printer engine are connected to one switch, and a storage area, a compressor, and a hard disk is connected to another switch.

Abstract: An information processor that is connected to at least one other information processor via a network, includes a detecting unit that detects an optional device to be used for information processing, as a target optional device, installed on the other information processor, an issuing unit that issues an access request to use the target optional device to the other information processor, a receiving unit that receives an access permission for access to the target optional device from the other information processor, and a processing unit that performs the information processing with the target optional device.

Abstract: A plotter repeats a process of standing by until the next line synchronization timing after data transfer for one line and transferring DMAC control information requesting data transfer for one line to an MCH for each line synchronization timing whereby image data for one page is transferred. Therefore, data transfer from the MCH to the plotter is processed by continuous posted requests, so that float with respect to a line period can be made longer without transmitting a plurality of data transfer requests from the plotter to the MCH in the split method. Thus, a high data transfer performance can be realized with an inexpensive circuit because the cost for mounting a buffer memory or the like on the circuit is not needed.

Abstract: A high-speed serial switch fabric is configured to perform a mapping of a traffic class that is capable of differentiating traffics onto a virtual channel. The high-speed serial switch fabric connects a plurality of devices. A traffic-class setting unit sets, when a conflict occurs between devices connected to the high-speed serial switch fabric, the traffic class for each of traffics in the devices having the conflict. A channel setting unit assigns each of set traffic classes to different virtual channels, and gives a priority of data communication to each of the set traffic classes.

Abstract: An information processing system includes a high-speed serial bus that transmits and receives data independently over communication channels via a tree-structured network including a point-to-point connection, and a control unit that issues a request command based on a request synchronization signal for data with a timing constraint on line synchronous transfer by a line synchronization signal to transmit a plurality of data, including the data with the timing constraint, simultaneously via the high-speed serial bus.

Abstract: A data transferring system based on the PCI Express standard in which power saving is realized is disclosed. In the data transferring system, a data transferring device transfers image data based on the PCI Express standard by synchronizing with a line synchronizing signal LSYNC. At this time, the data transferring device causes a period between packets (image data) to be transferred in one line cycle of the line synchronizing signal LSYNC to be shorter than a transition period “t1” which is required to transit from a link state L0 to a link state L0s and from the link state L0s to the link state L0. With this, the number of the transition periods “t1” is reduced and the period of the link state L0s is made long.

Abstract: An information processing apparatus includes a plurality of data communication devices via a high-speed serial bus with a plurality of traffics in different directions present between the data communication devices. A transfer-rate measuring unit measures a transfer rate of each of the traffics. A parameter adjusting unit adjusts a parameter for a data transfer in each of the traffics in such as manner that the transfer rate of each of the traffics measured by the transfer-rate measuring unit becomes a preset target value.

Abstract: A statistical-information generating unit monitors packet data output from a transaction layer that constitutes architecture of a PCI Express. The result of the monitored is feedback-controlled to a weight-information updating unit in real time, and is reflected in an arbitration table. A priority is set to the packet data corresponding to a quantity of the packet data actually transferred on a serial communication path.

Abstract: A high-speed serial switch fabric is configured to perform a mapping of a traffic class that is capable of differentiating traffics onto a virtual channel. The high-speed serial switch fabric connects a plurality of devices. A traffic-class setting unit sets, when a conflict occurs between devices connected to the high-speed serial switch fabric, the traffic class for each of traffics in the devices having the conflict. A channel setting unit assigns each of set traffic classes to different virtual channels, and gives a priority of data communication to each of the set traffic classes.

Abstract: An information processing system includes a high-speed serial bus that transmits and receives data independently over communication channels via a tree-structured network including a point-to-point connection, and a control unit that issues a request command based on a request synchronization signal for data with a timing constraint on line synchronous transfer by a line synchronization signal to transmit a plurality of data, including the data with the timing constraint, simultaneously via the high-speed serial bus.

Abstract: An information processor that is connected to at least one other information processor via a network, includes a detecting unit that detects an optional device to be used for information processing, as a target optional device, installed on the other information processor, an issuing unit that issues an access request to use the target optional device to the other information processor, a receiving unit that receives an access permission for access to the target optional device from the other information processor, and a processing unit that performs the information processing with the target optional device.

Abstract: An image forming apparatus includes an image input device that reads an image to obtain image data and a printer engine that forms an image on a medium based on image data. A bus of a PCI Express standard is used to transfer data. Storage areas serving as end points of the standard and hardware resources that transmit data and receive image data to and from the storage areas are connected to an identical switch according to the PCI Express standard. Specifically, an input/output area, an image input device, and a printer engine are connected to one switch, and a storage area, a compressor, and a hard disk is connected to another switch.

Abstract: A data transferring system, in which processes to match settings between devices mutually communicating are simplified, software for the processes is also simplified, and the amount of data to be processed is reduced, is disclosed. In a data transferring system of the PCI Express standard, when settings between facing ports of a switch and an end point are changed, a setting change is transmitted to the port of the end point being one of the facing ports by a configuration request. The port of the end point transmits the setting change to the port of the switch by a message request and the port of the switch executes the setting change. The port of the switch sends a completion message signifying the setting change completion to the port of the end point by a message request. The port of the end point executes the setting change.

Abstract: A data transferring system in which detecting a route from an upper position to a lower position on a tree structure is realized by hardware of communication devices and processes for detecting the above are simplified is disclosed. A root complex broadcasts a search message to a lower node on a tree structure. When a port of the node confirms and receives the search message, the port adds its own information, specifically, the device number of the port, to the data payload part of the search message and sends the search message including the information to a node (end point) located at the lowest position on the tree structure. When the end point receives the search message, the end point sends a reply message to the root complex. The device numbers of the ports where the search message passes through are attached to the reply message.

Abstract: A communication apparatus is disclosed that includes a transmission circuit configured to transmit transmission data to a communication counterpart; a reception circuit configured to receive reception data from the communication counterpart; a storage device configured as at least two buffers including a transmission buffer that stores the transmission data and a reception buffer that stores the reception data; and an address mapping unit configured to perform address mapping of the buffers including the transmission buffer and the reception buffer on the storage device, and adjust the storage capacity of the transmission buffer and the storage capacity of the reception buffer.

Abstract: A data transferring system based on the PCI Express standard in which power saving is realized is disclosed. In the data transferring system, a data transferring device transfers image data based on the PCI Express standard by synchronizing with a line synchronizing signal LSYNC. At this time, the data transferring device causes a period between packets (image data) to be transferred in one line cycle of the line synchronizing signal LSYNC to be shorter than a transition period “t1” which is required to transit from a link state L0 to a link state L0s and from the link state L0s to the link state L0. With this, the number of the transition periods “t1” is reduced and the period of the link state L0s is made long.

Abstract: A data transfer system using a high-speed serial interface system that forms a tree structure in which point-to-point communication channels are established for data sending and data receiving independently is provided. The data transfer system includes plural end points each having plural upper ports each of which is connected to a switch of an upper side, wherein each end point includes a port selecting part for selecting a port to be used according to an operation mode of the data transfer system so as to dynamically change the tree structure.

Abstract: An image forming system comprising a serial communication control part, an image input part, an image output part, an image processing part, a storage part, a printer controller, and a high-speed serial bus. The high-speed serial bus mutually couples the serial communication control part and at least one of the image input part, the image output part, the image processing part, the storage part and the printer controller.