Patents by Inventor Kosei Noda
Kosei Noda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240413166Abstract: An object is to obtain a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range, using a thin film transistor in which an oxide semiconductor layer is used. An analog circuit is formed with the use of a thin film transistor including an oxide semiconductor which has a function as a channel formation layer, has a hydrogen concentration of 5×1019 atoms/cm3 or lower, and substantially functions as an insulator in the state where no electric field is generated. Thus, a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range can be obtained.Type: ApplicationFiled: August 15, 2024Publication date: December 12, 2024Inventors: Shunpei YAMAZAKI, Jun KOYAMA, Atsushi HIROSE, Masashi TSUBUKU, Kosei NODA
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Patent number: 12109682Abstract: A robot control system includes circuitry configured to: acquire an input command value indicating a manipulation of a robot by a subject user; acquire a current state of the robot and a target state associated with the manipulation of the robot; determine a state difference between the current state and the target state; acquire from a learned model, a degree of distribution associated with a motion of the robot, based on the state difference, wherein the learned model is generated based on a past robot manipulation; set a level of assistance to be given during the manipulation of the robot by the subject user, based on the degree of distribution acquired; and generate an output command value for operating the robot, based on the input command value and the level of assistance.Type: GrantFiled: August 2, 2022Date of Patent: October 8, 2024Inventors: Masayuki Fujita, Takeshi Hatanaka, Junya Yamauchi, Kosei Noda, Keita Shimamoto, Koji Sokabe, Ryokichi Hirata, Masaru Adachi
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Publication number: 20240315026Abstract: According to one embodiment, in a semiconductor storage device, a plurality of second pillars each includes a first sub-pillar that is a single substance of a first insulating layer extending in the stacking direction in a lower layer side of a stacked body and a second sub-pillar arranged at a height position in an upper layer side of the stacked body to correspond to the first sub-pillar. The second sub-pillar includes a semiconductor layer extending in the stacking direction at the height position in the upper layer side of the stacked body, a second insulating layer covering a sidewall of the semiconductor layer, a third insulating layer covering a sidewall of the second insulating layer, and a fourth insulating layer that includes a different material from the second and third insulating layers and is interposed between the second and third insulating layers.Type: ApplicationFiled: March 8, 2024Publication date: September 19, 2024Applicant: Kioxia CorporationInventors: Ayumi WATARAI, Kenji TASHIRO, Kosei NODA
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Patent number: 12087866Abstract: A semiconductor device with stable electrical characteristics is provided. Alternatively, a semiconductor device having normally-off electrical characteristics is provided. A semiconductor device includes a gate electrode, a gate insulator, and an oxide semiconductor, the oxide semiconductor contains fluorine in a channel formation region, and a fluorine concentration in the channel formation region is higher than or equal to 1×1020 atoms/cm3 and lower than or equal to 1×1022 atoms/cm3. Note that fluorine is added by an ion implantation method.Type: GrantFiled: February 23, 2021Date of Patent: September 10, 2024Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Kosei Noda
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Publication number: 20240243204Abstract: An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit such as an LSI, a CPU, or a memory is manufactured using a thin film transistor in which a channel formation region is formed using an oxide semiconductor which becomes an intrinsic or substantially intrinsic semiconductor by removing impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than that of a silicon semiconductor, With use of a thin film transistor using a highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device with low power consumption due to leakage current can be realized.Type: ApplicationFiled: November 29, 2023Publication date: July 18, 2024Inventors: Shunpei YAMAZAKI, Jun KOYAMA, Hiroyuki MIYAKE, Kei TAKAHASHI, Kouhei TOYOTAKA, Masashi TSUBUKU, Kosei NODA, Hideaki KUWABARA
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Publication number: 20240203494Abstract: A semiconductor storage device includes a layered body with gate electrode layers and first insulating layers alternately stacked in a first direction; a first columnar body extending in the first direction; and a second columnar body extending in the first direction. The gate electrode layers include a first gate electrode layer and a second gate electrode layer. The second gate layer has a length in a second direction is less than a length of the first gate electrode layer in the second direction. The first columnar body includes a first conductive portion that penetrates the first gate electrode layer in the first direction. The second columnar body includes a second conductive portion that penetrates the second gate electrode layer and the first gate electrode layer in the first direction, and an insulating portion disposed between the first gate electrode layer and the second conductive portion.Type: ApplicationFiled: August 31, 2023Publication date: June 20, 2024Applicant: Kioxia CorporationInventor: Kosei NODA
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Publication number: 20240081084Abstract: A semiconductor memory device includes a substrate, a plurality of first conductive layers arranged in a first direction intersecting with a surface of the substrate, a memory structure including a first semiconductor layer opposed to the first conductive layers, a first wiring, a second conductive layer, a first insulating layer separating the plurality of first conductive layers in a second direction, a second insulating layer separating one or a plurality of the first conductive layers disposed on a side closest to the substrate, and a third insulating layer separating one or a plurality of the first conductive layers disposed on a side farthest from the substrate. The memory structure has a tapered shape having a width in the second direction decreasing with increasing distance from the substrate, and the third insulating layer has a tapered shape having a width in the second direction decreasing with decreasing distance from the substrate.Type: ApplicationFiled: June 20, 2023Publication date: March 7, 2024Applicant: Kioxia CorporationInventors: Yasuhito NAKAJIMA, Kosei NODA
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Publication number: 20240047583Abstract: A semiconductor device with stable electrical characteristics is provided. Alternatively, a semiconductor device having normally-off electrical characteristics is provided. A semiconductor device includes a gate electrode, a gate insulator, and an oxide semiconductor, the oxide semiconductor contains fluorine in a channel formation region, and a fluorine concentration in the channel formation region is higher than or equal to 1×1020 atoms/cm3 and lower than or equal to 1×1022 atoms/cm3. Note that fluorine is added by an ion implantation method.Type: ApplicationFiled: October 10, 2023Publication date: February 8, 2024Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventor: Kosei NODA
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Patent number: 11855194Abstract: A highly reliable semiconductor device which includes a thin film transistor having stable electric characteristics, and a manufacturing method thereof. In the manufacturing method of the semiconductor device which includes a thin film transistor where a semiconductor layer including a channel formation region is an oxide semiconductor layer, heat treatment which reduces impurities such as moisture to improve the purity of the oxide semiconductor layer and oxidize the oxide semiconductor layer (heat treatment for dehydration or dehydrogenation) is performed. Not only impurities such as moisture in the oxide semiconductor layer but also those existing in a gate insulating layer are reduced, and impurities such as moisture existing in interfaces between the oxide semiconductor layer and films provided over and under and in contact with the oxide semiconductor layer are reduced.Type: GrantFiled: October 13, 2021Date of Patent: December 26, 2023Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Miyuki Hosoba, Kosei Noda, Hiroki Ohara, Toshinari Sasaki, Junichiro Sakata
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Publication number: 20230411410Abstract: To reduce a leakage current of a transistor so that malfunction of a logic circuit can be suppressed. The logic circuit includes a transistor which includes an oxide semiconductor layer having a function of a channel formation layer and in which an off current is 1×10?13 A or less per micrometer in channel width. A first signal, a second signal, and a third signal that is a clock signal are input as input signals. A fourth signal and a fifth signal whose voltage states are set in accordance with the first to third signals which have been input are output as output signals.Type: ApplicationFiled: August 30, 2023Publication date: December 21, 2023Inventors: Shunpei YAMAZAKI, Jun KOYAMA, Masashi TSUBUKU, Kosei NODA
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Publication number: 20230395726Abstract: A logic circuit includes a thin film transistor having a channel formation region formed using an oxide semiconductor, and a capacitor having terminals one of which is brought into a floating state by turning off the thin film transistor. The oxide semiconductor has a hydrogen concentration of 5×1019 (atoms/cm3) or less and thus substantially serves as an insulator in a state where an electric field is not generated. Therefore, off-state current of a thin film transistor can be reduced, leading to suppressing the leakage of electric charge stored in a capacitor, through the thin film transistor. Accordingly, a malfunction of the logic circuit can be prevented. Further, the excessive amount of current which flows in the logic circuit can be reduced through the reduction of off-state current of the thin film transistor, resulting in low power consumption of the logic circuit.Type: ApplicationFiled: August 24, 2023Publication date: December 7, 2023Inventors: Shunpei YAMAZAKI, Jun KOYAMA, Masashi TSUBUKU, Kosei NODA
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Patent number: 11837461Abstract: An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit such as an LSI, a CPU, or a memory is manufactured using a thin film transistor in which a channel formation region is formed using an oxide semiconductor which becomes an intrinsic or substantially intrinsic semiconductor by removing impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than that of a silicon semiconductor. With use of a thin film transistor using a highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device with low power consumption due to leakage current can be realized.Type: GrantFiled: September 2, 2020Date of Patent: December 5, 2023Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Jun Koyama, Hiroyuki Miyake, Kei Takahashi, Kouhei Toyotaka, Masashi Tsubuku, Kosei Noda, Hideaki Kuwabara
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Publication number: 20230387136Abstract: An object is to provide a semiconductor device having a structure with which parasitic capacitance between wirings can be sufficiently reduced. An oxide insulating layer serving as a channel protective layer is formed over part of an oxide semiconductor layer overlapping with a gate electrode layer. In the same step as formation of the oxide insulating layer, an oxide insulating layer covering a peripheral portion of the oxide semiconductor layer is formed. The oxide insulating layer which covers the peripheral portion of the oxide semiconductor layer is provided to increase the distance between the gate electrode layer and a wiring layer formed above or in the periphery of the gate electrode layer, whereby parasitic capacitance is reduced.Type: ApplicationFiled: August 9, 2023Publication date: November 30, 2023Inventors: Shunpei Yamazaki, Hiroki Ohara, Toshinari Sasaki, Kosei Noda, Hideaki Kuwabara
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Patent number: 11832453Abstract: According to one embodiment, a semiconductor storage device includes a stacked body above a substrate. The stacked body includes a first stacked region in which a first insulating layer and a second insulating layer are alternately stacked and a second stacked region in which a conductive layer and the first insulating layer are alternately stacked. The semiconductor storage device includes a memory pillar that extends through the second stacked region of the stacked body in a stacking direction. The second insulating layer comprising a first insulating material within the first stacked region and a second insulating material on ends of the second insulating layer in a direction intersecting to the stacking direction.Type: GrantFiled: February 23, 2022Date of Patent: November 28, 2023Assignee: Kioxia CorporationInventor: Kosei Noda
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Patent number: 11756966Abstract: To reduce a leakage current of a transistor so that malfunction of a logic circuit can be suppressed. The logic circuit includes a transistor which includes an oxide semiconductor layer having a function of a channel formation layer and in which an off current is 1×10?13 A or less per micrometer in channel width. A first signal, a second signal, and a third signal that is a clock signal are input as input signals. A fourth signal and a fifth signal whose voltage states are set in accordance with the first to third signals which have been input are output as output signals.Type: GrantFiled: November 4, 2022Date of Patent: September 12, 2023Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Jun Koyama, Masashi Tsubuku, Kosei Noda
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Patent number: 11742432Abstract: A logic circuit includes a thin film transistor having a channel formation region formed using an oxide semiconductor, and a capacitor having terminals one of which is brought into a floating state by turning off the thin film transistor. The oxide semiconductor has a hydrogen concentration of 5×1019 (atoms/cm3) or less and thus substantially serves as an insulator in a state where an electric field is not generated. Therefore, off-state current of a thin film transistor can be reduced, leading to suppressing the leakage of electric charge stored in a capacitor, through the thin film transistor. Accordingly, a malfunction of the logic circuit can be prevented. Further, the excessive amount of current which flows in the logic circuit can be reduced through the reduction of off-state current of the thin film transistor, resulting in low power consumption of the logic circuit.Type: GrantFiled: December 30, 2021Date of Patent: August 29, 2023Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Jun Koyama, Masashi Tsubuku, Kosei Noda
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Patent number: 11728350Abstract: An object is to provide a semiconductor device having a structure with which parasitic capacitance between wirings can be sufficiently reduced. An oxide insulating layer serving as a channel protective layer is formed over part of an oxide semiconductor layer overlapping with a gate electrode layer. In the same step as formation of the oxide insulating layer, an oxide insulating layer covering a peripheral portion of the oxide semiconductor layer is formed. The oxide insulating layer which covers the peripheral portion of the oxide semiconductor layer is provided to increase the distance between the gate electrode layer and a wiring layer formed above or in the periphery of the gate electrode layer, whereby parasitic capacitance is reduced.Type: GrantFiled: February 16, 2022Date of Patent: August 15, 2023Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hiroki Ohara, Toshinari Sasaki, Kosei Noda, Hideaki Kuwabara
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Patent number: 11631756Abstract: A semiconductor device is manufactured using a transistor in which an oxide semiconductor is included in a channel region and variation in electric characteristics due to a short-channel effect is less likely to be caused. The semiconductor device includes an oxide semiconductor film having a pair of oxynitride semiconductor regions including nitrogen and an oxide semiconductor region sandwiched between the pair of oxynitride semiconductor regions, a gate insulating film, and a gate electrode provided over the oxide semiconductor region with the gate insulating film positioned therebetween. Here, the pair of oxynitride semiconductor regions serves as a source region and a drain region of the transistor, and the oxide semiconductor region serves as the channel region of the transistor.Type: GrantFiled: October 19, 2020Date of Patent: April 18, 2023Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yuta Endo, Toshinari Sasaki, Kosei Noda
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Publication number: 20230064813Abstract: To reduce a leakage current of a transistor so that malfunction of a logic circuit can be suppressed. The logic circuit includes a transistor which includes an oxide semiconductor layer having a function of a channel formation layer and in which an off current is 1×10?13 A or less per micrometer in channel width. A first signal, a second signal, and a third signal that is a clock signal are input as input signals. A fourth signal and a fifth signal whose voltage states are set in accordance with the first to third signals which have been input are output as output signals.Type: ApplicationFiled: November 4, 2022Publication date: March 2, 2023Inventors: Shunpei YAMAZAKI, Jun KOYAMA, Masashi TSUBUKU, Kosei NODA
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Publication number: 20220371203Abstract: A robot control system includes circuitry configured to: acquire an input command value indicating a manipulation of a robot by a subject user; acquire a current state of the robot and a target state associated with the manipulation of the robot; determine a state difference between the current state and the target state; acquire from a learned model, a degree of distribution associated with a motion of the robot, based on the state difference, wherein the learned model is generated based on a past robot manipulation; set a level of assistance to be given during the manipulation of the robot by the subject user, based on the degree of distribution acquired; and generate an output command value for operating the robot, based on the input command value and the level of assistance.Type: ApplicationFiled: August 2, 2022Publication date: November 24, 2022Inventors: Masayuki FUJITA, Takeshi HATANAKA, Junya YAMAUCHI, Kosei NODA, Keita SHIMAMOTO, Koji SOKABE, Ryokichi HIRATA, Masaru ADACHI