Patents by Inventor Kosei Noda
Kosei Noda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10074747Abstract: An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit such as an LSI, a CPU, or a memory is manufactured using a thin film transistor in which a channel formation region is formed using an oxide semiconductor which becomes an intrinsic or substantially intrinsic semiconductor by removing impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than that of a silicon semiconductor. With use of a thin film transistor using a highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device with low power consumption due to leakage current can be realized.Type: GrantFiled: December 8, 2016Date of Patent: September 11, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Jun Koyama, Hiroyuki Miyake, Kei Takahashi, Kouhei Toyotaka, Masashi Tsubuku, Kosei Noda, Hideaki Kuwabara
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Patent number: 10061172Abstract: A liquid crystal display device includes: a driver circuit portion; a pixel portion; a signal generation circuit for generating a control signal for driving the driver circuit portion and an image signal which is supplied to the pixel portion; a memory circuit; a comparison circuit for detecting a difference of image signals for a series of frame periods among image signals stored for respective frame periods in the memory circuit; a selection circuit which selects and outputs the image signals for the series of frame periods when the difference is detected in the comparison circuit; and a display control circuit which supplies the control signal and the image signals output from the selection circuit, to the driver circuit portion when the difference is detected in the comparison circuit, and stops supplying the control signal to the driver circuit portion when the difference is not detected in the comparison circuit.Type: GrantFiled: October 14, 2010Date of Patent: August 28, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Jun Koyama, Hiroyuki Miyake, Masashi Tsubuku, Kosei Noda
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Publication number: 20180174891Abstract: An object is to provide a semiconductor device with reduced standby power. A transistor including an oxide semiconductor as an active layer is used as a switching element, and supply of a power supply voltage to a circuit in an integrated circuit is controlled by the switching element. Specifically, when the circuit is in an operation state, supply of the power supply voltage to the circuit is performed by the switching element, and when the circuit is in a stop state, supply of the power supply voltage to the circuit is stopped by the switching element. In addition, the circuit supplied with the power supply voltage includes a semiconductor element which is a minimum unit included in an integrated circuit formed using a semiconductor. Further, the semiconductor included in the semiconductor element contains silicon having crystallinity (crystalline silicon).Type: ApplicationFiled: February 13, 2018Publication date: June 21, 2018Inventors: Yutaka SHIONOIRI, Kosei NODA
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Patent number: 10002891Abstract: Exemplary semiconductor devices include eight transistors and two capacitors interconnected in specific configurations. A display device may include a driver circuit having such a semiconductor device. An electronic device may also include such a semiconductor device and an input unit, LED lamp or speaker.Type: GrantFiled: March 27, 2017Date of Patent: June 19, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Jun Koyama, Masashi Tsubuku, Kosei Noda
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Publication number: 20180151744Abstract: A highly reliable semiconductor device having stable electric characteristics is provided by suppressing, in a transistor including an oxide semiconductor film, diffusion of indium into an insulating film in contact with the oxide semiconductor film and improving the characteristics of the interface between the oxide semiconductor film and the insulating film. In an oxide semiconductor film containing indium, the indium concentration at a surface is decreased, thereby preventing diffusion of indium into an insulating film on and in contact with the oxide semiconductor film. By decreasing the indium concentration at the surface of the oxide semiconductor film, a layer which does not substantially contain indium can be formed at the surface. By using this layer as part of the insulating film, the characteristics of the interface between the oxide semiconductor film and the insulating film in contact with the oxide semiconductor film are improved.Type: ApplicationFiled: January 25, 2018Publication date: May 31, 2018Inventors: Kosei NODA, Noriyoshi SUZUKI
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Patent number: 9978855Abstract: One embodiment of the present invention is a semiconductor device at least including an oxide semiconductor film, a gate insulating film in contact with the oxide semiconductor film, and a gate electrode overlapping with the oxide semiconductor film with the gate insulating film therebetween. The oxide semiconductor film has a spin density lower than 9.3×1016 spins/cm3 and a carrier density lower than 1×1015/cm3. The spin density is calculated from a peak of a signal detected at a g value (g) of around 1.93 by electron spin resonance spectroscopy. The oxide semiconductor film is formed by a sputtering method while bias power is supplied to the substrate side and self-bias voltage is controlled, and then subjected to heat treatment.Type: GrantFiled: September 30, 2016Date of Patent: May 22, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kosei Noda, Suzunosuke Hiraishi
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Publication number: 20180138211Abstract: An object is to provide a semiconductor device having a structure with which parasitic capacitance between wirings can be sufficiently reduced. An oxide insulating layer serving as a channel protective layer is formed over part of an oxide semiconductor layer overlapping with a gate electrode layer. In the same step as formation of the oxide insulating layer, an oxide insulating layer covering a peripheral portion of the oxide semiconductor layer is formed. The oxide insulating layer which covers the peripheral portion of the oxide semiconductor layer is provided to increase the distance between the gate electrode layer and a wiring layer formed above or in the periphery of the gate electrode layer, whereby parasitic capacitance is reduced.Type: ApplicationFiled: October 6, 2017Publication date: May 17, 2018Inventors: Shunpei Yamazaki, Hiroki Ohara, Toshinari Sasaki, Kosei Noda, Hideaki Kuwabara
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Patent number: 9960279Abstract: Hydrogen concentration and oxygen vacancies in an oxide semiconductor film are reduced. Reliability of a semiconductor device which includes a transistor using an oxide semiconductor film is improved. One embodiment of the present invention is a semiconductor device which includes a base insulating film; an oxide semiconductor film formed over the base insulating film; a gate insulating film formed over the oxide semiconductor film; and a gate electrode overlapping with the oxide semiconductor film with the gate insulating film provided therebetween. The base insulating film shows a signal at a g value of 2.01 by electron spin resonance. The oxide semiconductor film does not show a signal at a g value of 1.93 by electron spin resonance.Type: GrantFiled: December 4, 2014Date of Patent: May 1, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Toshinari Sasaki, Kosei Noda, Yuhei Sato, Yuta Endo
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Patent number: 9959822Abstract: In a liquid crystal display device including a plurality of pixels in a display portion and configured to performed display in a plurality of frame periods, each of the frame periods includes a writing period and a holding period, and after an image signal is input to each of the plurality of pixels in the writing period, a transistor included in each of the plurality of pixels is turned off and the image signal is held for at least 30 seconds in the holding period. The pixel includes a semiconductor layer including an oxide semiconductor layer, and the oxide semiconductor layer has a carrier concentration of less than 1×1014/cm3.Type: GrantFiled: April 21, 2016Date of Patent: May 1, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Ryo Arasawa, Jun Koyama, Masashi Tsubuku, Kosei Noda
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Patent number: 9947695Abstract: Exemplary semiconductor devices include eight transistors and two capacitors interconnected in specific configurations. A display device may include a driver circuit having such a semiconductor device. An electronic device may also include such a semiconductor device and an input unit, LED lamp or speaker.Type: GrantFiled: October 24, 2016Date of Patent: April 17, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Jun Koyama, Masashi Tsubuku, Kosei Noda
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Publication number: 20180090086Abstract: In a liquid crystal display device including a plurality of pixels in a display portion and configured to performed display in a plurality of frame periods, each of the frame periods includes a writing period and a holding period, and after an image signal is input to each of the plurality of pixels in the writing period, a transistor included in each of the plurality of pixels is turned off and the image signal is held for at least 30 seconds in the holding period. The pixel includes a semiconductor layer including an oxide semiconductor layer, and the oxide semiconductor layer has a carrier concentration of less than 1×1014/cm3.Type: ApplicationFiled: November 28, 2017Publication date: March 29, 2018Inventors: Shunpei YAMAZAKI, Ryo ARASAWA, Jun KOYAMA, Masashi TSUBUKU, Kosei NODA
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Patent number: 9929280Abstract: A highly reliable semiconductor device having stable electric characteristics is provided by suppressing, in a transistor including an oxide semiconductor film, diffusion of indium into an insulating film in contact with the oxide semiconductor film and improving the characteristics of the interface between the oxide semiconductor film and the insulating film. In an oxide semiconductor film containing indium, the indium concentration at a surface is decreased, thereby preventing diffusion of indium into an insulating film on and in contact with the oxide semiconductor film. By decreasing the indium concentration at the surface of the oxide semiconductor film, a layer which does not substantially contain indium can be formed at the surface. By using this layer as part of the insulating film, the characteristics of the interface between the oxide semiconductor film and the insulating film in contact with the oxide semiconductor film are improved.Type: GrantFiled: August 18, 2016Date of Patent: March 27, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kosei Noda, Noriyoshi Suzuki
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Patent number: 9929281Abstract: A transistor includes a gate, a source, and a drain, the gate is electrically connected to the source or the drain, a first signal is input to one of the source and the drain, and an oxide semiconductor layer whose carrier concentration is 5×1014/cm3 or less is used for a channel formation layer. A capacitor includes a first electrode and a second electrode, the first electrode is electrically connected to the other of the source and the drain of the transistor, and a second signal which is a clock signal is input to the second electrode. A voltage of the first signal is stepped up or down to obtain a third signal which is output as an output signal through the other of the source and the drain of the transistor.Type: GrantFiled: August 29, 2016Date of Patent: March 27, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hiroyuki Miyake, Masashi Tsubuku, Kosei Noda
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Patent number: 9917204Abstract: A semiconductor device of stable electrical characteristics, whose oxygen vacancies in a metal oxide is reduced, is provided. The semiconductor device includes a gate electrode, a gate insulating film over the gate electrode, a first metal oxide film over the gate insulating film, a source electrode and a drain electrode which are in contact with the first metal oxide film, and a passivation film over the source electrode and the drain electrode. A first insulating film, a second metal oxide film, and a second insulating film are stacked sequentially in the passivation film.Type: GrantFiled: February 16, 2016Date of Patent: March 13, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Tadashi Nakano, Mai Sugikawa, Kosei Noda
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Patent number: 9893195Abstract: A highly reliable transistor which includes an oxide semiconductor and has high field-effect mobility and in which a variation in threshold voltage is small is provided. By using the transistor, a high-performance semiconductor device, which has been difficult to realize, is provided. The transistor includes an oxide semiconductor film which contains two or more kinds, preferably three or more kinds of elements selected from indium, tin, zinc, and aluminum. The oxide semiconductor film is formed in a state where a substrate is heated. Further, oxygen is supplied to the oxide semiconductor film with an adjacent insulating film and/or by ion implantation in a manufacturing process of the transistor, so that oxygen deficiency which generates a carrier is reduced as much as possible. In addition, the oxide semiconductor film is highly purified in the manufacturing process of the transistor, so that the concentration of hydrogen is made extremely low.Type: GrantFiled: December 22, 2014Date of Patent: February 13, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kosei Noda, Shunpei Yamazaki, Tatsuya Honda, Yusuke Sekine, Hiroyuki Tomatsu
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Patent number: 9871143Abstract: A semiconductor device that is suitable for miniaturization. A method for manufacturing a semiconductor device includes the steps of forming a semiconductor, forming a first conductor over the semiconductor, performing a second process on the first conductor so as to form a conductor according to a first pattern, forming a first insulator over the conductor having the first pattern, forming an opening in the first insulator, performing a third process on the conductor having the first pattern in the opening so as to form a first electrode and a second electrode and to expose the semiconductor, forming a second insulator over the first insulator, an inner wall of the opening, and an exposed portion of the semiconductor, forming a second conductor over the second insulator, and performing a fourth process on the second conductor so as to form a third electrode.Type: GrantFiled: March 13, 2015Date of Patent: January 16, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yuta Endo, Kosei Noda
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Publication number: 20170358683Abstract: An object is to provide a memory device including a memory element that can be operated without problems by a thin film transistor with a low off-state current. Provided is a memory device in which a memory element including at least one thin film transistor that includes an oxide semiconductor layer is arranged as a matrix. The thin film transistor including an oxide semiconductor layer has a high field effect mobility and low off-state current, and thus can be operated favorably without problems. In addition, the power consumption can be reduced. Such a memory device is particularly effective in the case where the thin film transistor including an oxide semiconductor layer is provided in a pixel of a display device because the memory device and the pixel can be formed over one substrate.Type: ApplicationFiled: August 8, 2017Publication date: December 14, 2017Inventors: Shunpei YAMAZAKI, Masashi TSUBUKU, Kosei NODA, Kouhei TOYOTAKA, Kazunori WATANABE, Hikaru HARADA
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Patent number: 9842939Abstract: In a transistor having a top-gate structure in which a gate electrode layer overlaps with an oxide semiconductor layer which faints a channel region with a gate insulating layer interposed therebetween, when a large amount of hydrogen is contained in the insulating layer, hydrogen is diffused into the oxide semiconductor layer because the insulating layer is in contact with the oxide semiconductor layer; thus, electric characteristics of the transistor are degraded. An object is to provide a semiconductor device having favorable electric characteristics. An insulating layer in which the concentration of hydrogen is less than 6×1020 atoms/cm3 is used for the insulating layer being in contact with oxide semiconductor layer which forms the channel region. Using the insulating layer, diffusion of hydrogen can be prevented and a semiconductor device having favorable electric characteristics can be provided.Type: GrantFiled: September 8, 2016Date of Patent: December 12, 2017Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yuta Endo, Toshinari Sasaki, Kosei Noda, Mizuho Sato, Mitsuhiro Ichijo, Toshiya Endo
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Patent number: 9812544Abstract: To manufacture a transistor whose threshold voltage is controlled without using a backgate electrode, a circuit for controlling the threshold voltage, and an impurity introduction method. To manufacture a semiconductor device having favorable electrical characteristics, high reliability, and low power consumption using the transistor. A gate electrode including a tungsten oxide film whose composition is controlled is used. The composition or the like is adjusted by a film formation method of the tungsten oxide film, whereby the work function can be controlled. By using the tungsten oxide film whose work function is controlled as part of the gate electrode, the threshold of the transistor can be controlled. Using the transistor whose threshold voltage is controlled, a semiconductor device having favorable electrical characteristics, high reliability, and low power consumption can be manufactured.Type: GrantFiled: November 9, 2015Date of Patent: November 7, 2017Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yuta Endo, Toshinari Sasaki, Kosei Noda, Hitomi Sato, Yuhei Sato
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Publication number: 20170317112Abstract: An object is to obtain a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range, using a thin film transistor in which an oxide semiconductor layer is used. An analog circuit is formed with the use of a thin film transistor including an oxide semiconductor which has a function as a channel formation layer, has a hydrogen concentration of 5×1019 atoms/cm3 or lower, and substantially functions as an insulator in the state where no electric field is generated. Thus, a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range can be obtained.Type: ApplicationFiled: July 18, 2017Publication date: November 2, 2017Inventors: Shunpei YAMAZAKI, Jun KOYAMA, Atsushi HIROSE, Masashi TSUBUKU, Kosei NODA