Patents by Inventor Kostas I. Papathomas

Kostas I. Papathomas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9756724
    Abstract: A circuitized substrate which includes a conductive paste for providing electrical connections. The paste, in one embodiment, includes a metallic component including nano-particles and may include additional elements such as solder or other metal micro-particles, as well as a conducting polymer and organic. The particles of the paste composition sinter and, depending on what additional elements are added, melt as a result of lamination to thereby form effective contiguous circuit paths through the paste. A method of making such a substrate is also provided, as is an electrical assembly utilizing the substrate and including an electronic component such as a semiconductor chip coupled thereto.
    Type: Grant
    Filed: October 4, 2011
    Date of Patent: September 5, 2017
    Inventors: Rabindra N. Das, Kostas I. Papathomas, Voya R. Markovich
  • Publication number: 20120247822
    Abstract: A substrate for use in a laminated chip carrier (LCC) and a system in package (SiP) device having a coreless buildup layer and at least one metal and at least one dielectric layer. The coreless buildup dielectric layers can include thermoset and thermoplastic resin.
    Type: Application
    Filed: March 28, 2011
    Publication date: October 4, 2012
    Applicant: Endicott Interconnect Technologies, Inc.
    Inventors: James W. Fuller, JR., Jeffrey Knight, Voya R. Markovich, Kostas I. Papathomas
  • Patent number: 8211790
    Abstract: A multilayered circuitized substrate including a plurality of dielectric layers each comprised of a p-aramid paper impregnated with a halogen-free, low moisture absorptivity resin including an inorganic filler but not including continuous or semi-continuous fiberglass fibers as part thereof, and a first circuitized layer positioned on a first of the dielectric layers. A method of making this substrate is also provided.
    Type: Grant
    Filed: March 2, 2009
    Date of Patent: July 3, 2012
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Robert M. Japp, Voya R. Markovich, Kostas I. Papathomas, Mark D. Poliks
  • Publication number: 20120017437
    Abstract: A circuitized substrate which includes a conductive paste for providing electrical connections. The paste, in one embodiment, includes a metallic component including nano-particles and may include additional elements such as solder or other metal micro-particles, as well as a conducting polymer and organic. The particles of the paste composition sinter and, depending on what additional elements are added, melt as a result of lamination to thereby form effective contiguous circuit paths through the paste. A method of making such a substrate is also provided, as is an electrical assembly utilizing the substrate and including an electronic component such as a semiconductor chip coupled thereto.
    Type: Application
    Filed: October 4, 2011
    Publication date: January 26, 2012
    Applicant: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
    Inventors: Rabindra N. Das, Kostas I. Papathomas, Voya R. Markovich
  • Publication number: 20120012553
    Abstract: A method for making a leadless chip carrier (LCC) for use in electronic packages having a core layer stripped of copper cladding, containing drilled clearance holes within, a layer of resin coated copper (RCC) placed on the upper surface of the core layer and a second layer of RCC placed on the lower surface of the core layer. The layers are laminated together with the RCC filling the clearance holes during lamination. A pattern is etched on the RCC and vias are drilled through the filled clearance holes and pre-plated with seed copper layers. The seed copper layers in the vias are then covered by a layer of copper plating to meet the requirements of the core buildup layer, and resin inhibiting conductive anodic filament (CAF) growth within the structure.
    Type: Application
    Filed: July 16, 2010
    Publication date: January 19, 2012
    Applicant: Endicott Interconnect Technologies, Inc.
    Inventors: Robert M. Japp, Kostas I. Papathomas, Cheryl Palomaki
  • Patent number: 8084863
    Abstract: A circuitized substrate including a dielectric layer having a p-aramid paper impregnated with a halogen-free, low moisture absorptivity resin and not including continuous or semi-continuous fiberglass fibers as part thereof, and a first circuitized layer positioned on the dielectric layer. A method of making this substrate is also provided.
    Type: Grant
    Filed: April 10, 2008
    Date of Patent: December 27, 2011
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Robert M. Japp, Voya R. Markovich, Kostas I. Papathomas, Mark D. Poliks
  • Patent number: 8063315
    Abstract: A circuitized substrate which includes a conductive paste for providing electrical connections. The paste, in one embodiment, includes a metallic component including nano-particles and may include additional elements such as solder or other metal micro-particles, as well as a conducting polymer and organic. The particles of the paste composition sinter and, depending on what additional elements are added, melt as a result of lamination to thereby form effective contiguous circuit paths through the paste. A method of making such a substrate is also provided, as is an electrical assembly utilizing the substrate and including an electronic component such as a semiconductor chip coupled thereto.
    Type: Grant
    Filed: May 23, 2007
    Date of Patent: November 22, 2011
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Rabindra N. Das, Kostas I. Papathomas, Voya R. Markovich
  • Publication number: 20110207866
    Abstract: A dielectric composition for forming a dielectric layer usable in circuitized substrates such as PCBs, chip carriers and the like. The composition includes at least three resins: a halogen-free flame retardant, methyl ethyl ketone (prior to final layer formation), manganese octoate, and a coupling agent. The composition does not include a halogen or a fluoropolymer as part thereof. Dielectric layers formed from the composition are capable of withstanding the relatively high temperatures associated with lead-free solder applications. The composition may or may not include inorganic filler as part thereof.
    Type: Application
    Filed: February 25, 2010
    Publication date: August 25, 2011
    Inventors: Robert M. Japp, Kostas I. Papathomas
  • Patent number: 7931830
    Abstract: A dielectric composition which is adapted for combining with a supporting material ( e.g., fiber-glass cloth) to form a dielectric layer usable in circuitized such as PCBs, chip carriers and the like. As such a layer, it includes a resin, a predetermined percentage by weight of a filler, and, significantly, only a minor amount of bromine. A circuitized substrate comprised of one or more of these dielectric layers and one or more conductive layers is also provided.
    Type: Grant
    Filed: November 3, 2005
    Date of Patent: April 26, 2011
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Robert M. Japp, Voya R. Markovich, Kostas I. Papathomas
  • Publication number: 20110017498
    Abstract: A photosensitive dielectric composition adapted for forming a dielectric film layer for use in a circuitized substrate is provided according to one embodiment of the invention, the composition including an epoxide bearing component including at least one polyepoxide resin curable by electromagnetic radiation, a cyanate ester, a flexibilizer, a nanostructured toughener, a photoinitiator in a predetermined amount by weight of the resin component, and a ceramic filler, the photosensitive dielectric composition forming the dielectric film layer having no solvent therein. In an alternative embodiment, a heat activated dielectric composition is provided which is curable by heat and includes an epoxide bearing component including at least one polyepoxide resin curable by heat, a cyanate ester, a flexibilizer, a nanostructured toughener, a heat activated curing agent for accelerating reaction of the cyanate ester and polyepoxide resin components, and a ceramic filler.
    Type: Application
    Filed: July 27, 2009
    Publication date: January 27, 2011
    Inventors: John M. Lauffer, Voya R. Markovich, Kostas I. Papathomas
  • Patent number: 7646098
    Abstract: A multilayered circuitized substrate including a plurality of dielectric layers each comprised of a p-aramid paper impregnated with a halogen-free, low moisture absorptivity resin including an inorganic filler but not including continuous or semi-continuous fiberglass fibers as part thereof, and a first circuitized layer positioned on a first of the dielectric layers. A method of making this substrate is also provided.
    Type: Grant
    Filed: April 10, 2008
    Date of Patent: January 12, 2010
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Robert M. Japp, Voya R. Markovich, Kostas I. Papathomas, Mark D. Poliks
  • Publication number: 20090258161
    Abstract: A circuitized substrate including a dielectric layer having a p-aramid paper impregnated with a halogen-free, low moisture absorptivity resin and not including continuous or semi-continuous fiberglass fibers as part thereof, and a first circuitized layer positioned on the dielectric layer. A method of making this substrate is also provided.
    Type: Application
    Filed: March 2, 2009
    Publication date: October 15, 2009
    Inventors: Robert M. Japp, Voya R. Markovich, Kostas I. Papathomas, Mark D. Poliks
  • Publication number: 20090241332
    Abstract: A circuitized substrate and method of making same in which a first plurality of holes are formed within two bonded dielectric layers and then made conductive, e.g., plated. The substrate also includes third and fourth dielectric layers bonded to the first and second with a plurality of continuous electrically conductive thru holes extending through all four dielectric layers. Conductive paste is positioned within the thru holes for providing electrical connections between desired conductive layers of the substrate and outer layers as well. A circuitized substrate assembly and method of making same are also provided.
    Type: Application
    Filed: March 28, 2008
    Publication date: October 1, 2009
    Inventors: John M. Lauffer, Roy H. Magnuson, Voya R. Markovich, James P. Paoletti, Kostas I. Papathomas, Rajinder S. Rai
  • Publication number: 20090173426
    Abstract: A multilayered circuitized substrate including a plurality of dielectric layers each comprised of a p-aramid paper impregnated with a halogen-free, low moisture absorptivity resin including an inorganic filler but not including continuous or semi-continuous fiberglass fibers as part thereof, and a first circuitized layer positioned on a first of the dielectric layers. A method of making this substrate is also provided.
    Type: Application
    Filed: March 2, 2009
    Publication date: July 9, 2009
    Inventors: Robert M. Japp, Voya R. Markovich, Kostas I. Papathomas, Mark D. Poliks
  • Patent number: 7541265
    Abstract: A material for use as part of an internal capacitor within a circuitized substrate includes a polymer (e.g., a cycloaliphatic epoxy or phenoxy based) resin and a quantity of nano-powders of ferroelectric ceramic material (e.g., barium titanate) having a particle size substantially in the range of from about 0.01 microns to about 0.90 microns and a surface area for selected ones of said particles within the range of from about 2.0 to about 20 square meters per gram. A circuitized substrate adapted for using such a material and capacitor therein and a method of making such a substrate are also provided. An electrical assembly (substrate and at least one electrical component) and an information handling system (e.g., personal computer) are also provided.
    Type: Grant
    Filed: January 10, 2005
    Date of Patent: June 2, 2009
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Rabindra N. Das, John M. Lauffer, Kostas I. Papathomas, Mark D. Poliks
  • Patent number: 7470990
    Abstract: A circuitized substrate including a composite layer including a first dielectric sub-layer including a plurality of fibers having a low coefficient of thermal expansion and a second dielectric sub-layer of a low moisture absorptivity resin, the second dielectric sub-layer not including continuous or semi-continuous fibers or the like as part thereof. The substrate further includes at least one electrically conductive layer as part thereof. An electrical assembly and a method of making the substrate are also provided, as is an information handling system (e.g., computer) incorporating the circuitized substrate of the invention as part thereof.
    Type: Grant
    Filed: March 23, 2005
    Date of Patent: December 30, 2008
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Robert M. Japp, Irving Memis, Kostas I. Papathomas
  • Patent number: 7429789
    Abstract: A dielectric composition for forming a dielectric layer usable in circuitized substrates such as PCBs, chip carriers and the like, the composition including at least two fluoropolymers and two inorganic fillers. A circuitized substrate including at least one such dielectric layer and at least one conductive layer thereon is also provided.
    Type: Grant
    Filed: March 28, 2006
    Date of Patent: September 30, 2008
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Robert M. Japp, Voya R. Markovich, Kostas I. Papathomas
  • Patent number: 7416972
    Abstract: A method of making a circuitized substrate including a composite layer including a first dielectric sub-layer including a plurality of fibers having a low coefficient of thermal expansion and a second dielectric sub-layer of a low moisture absorptivity resin, the second dielectric sub-layer not including continuous or semi-continuous fibers or the like as part thereof. The substrate further includes at least one electrically conductive layer as part thereof.
    Type: Grant
    Filed: April 5, 2007
    Date of Patent: August 26, 2008
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Robert M. Japp, Irving Memis, Kostas I. Papathomas
  • Publication number: 20080191353
    Abstract: A multilayered circuitized substrate including a plurality of dielectric layers each comprised of a p-aramid paper impregnated with a halogen-free, low moisture absorptivity resin including an inorganic filler but not including continuous or semi-continuous fiberglass fibers as part thereof, and a first circuitized layer positioned on a first of the dielectric layers. A method of making this substrate is also provided.
    Type: Application
    Filed: April 10, 2008
    Publication date: August 14, 2008
    Applicant: Endicott Interconnect Technologies, Inc.
    Inventors: Robert M. Japp, Voya R. Markovich, Kostas I. Papathomas, Mark D. Poliks
  • Publication number: 20080191354
    Abstract: A circuitized substrate including a dielectric layer having a p-aramid paper impregnated with a halogen-free, low moisture absorptivity resin and not including continuous or semi-continuous fiberglass fibers as part thereof, and a first circuitized layer positioned on the dielectric layer. A method of making this substrate is also provided.
    Type: Application
    Filed: April 10, 2008
    Publication date: August 14, 2008
    Applicant: Endicott Interconnect Technologies, Inc.
    Inventors: Robert M. Japp, Voya R. Markovich, Kostas I. Papathomas, Mark D. Poliks