Patents by Inventor Kosuke Miyazaki
Kosuke Miyazaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11940708Abstract: Provided is an optical modulator that can be driven at lower voltage through the use of differential signal output. An optical modulator includes a substrate 1 and optical waveguides (21, 22) and a control electrode that are formed on the substrate, in which the optical waveguide includes Mach-Zehnder type optical waveguide, the control electrode is provided with two ground electrodes sandwiching three signal electrodes; the three signal electrodes are constituted by second and third signal electrodes that sandwich a first signal electrode, and have a wiring structure in which one modulation signal of the differential signal is applied to the first signal electrode, and the other modulation signal of the differential signal is applied to the second and third signal electrodes; and one branched waveguide (21) out of two Mach-Zehnder type optical waveguides is disposed between the first and second signal electrodes, and the other branched waveguide (22) is disposed between the first and third signal electrodes.Type: GrantFiled: September 26, 2019Date of Patent: March 26, 2024Assignee: SUMITOMO OSAKA CEMENT CO., LTD.Inventors: Norikazu Miyazaki, Kosuke Okahashi, Masayuki Motoya
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Patent number: 11935919Abstract: A method for manufacturing a semiconductor device includes forming, on first and second impurity layers on a termination region side, an insulating layer, forming a first metal film and a second metal film in this order on the insulating layer and a drift layer, performing dry etching on the first and second metal films all together so that a position of a first end of a metallized layer, which is a remaining part of the first metal film, in the interface region on the termination region side and a position of a second end of an electrode, which is a remaining part of the second metal film, in the interface region on the terminal region side are the same in plan view. The first and second ends are closer to the active region than an end of the second impurity layer on the termination region side in plan view.Type: GrantFiled: August 1, 2022Date of Patent: March 19, 2024Assignee: Mitsubishi Electric CorporationInventors: Yoshinori Matsuno, Yasushi Takaki, Kensuke Taguchi, Kosuke Miyazaki
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Publication number: 20230420695Abstract: A catalyst for fuel cells that contains a carbon powder carrier and catalyst particles carried on the carbon powder carrier, the catalyst particles being Pt alloy particles, the catalyst for fuel cells having 0.65 mmol/g or more of hydrophilic groups, and a Pt elution amount when 0.5 g of the catalyst for fuel cells is immersed in 30 ml of a 0.5 mol/L aqueous sulfuric acid solution and retained for 100 hours at room temperature under stirring being 0.625 mg or less per g of the catalyst for fuel cells.Type: ApplicationFiled: November 24, 2021Publication date: December 28, 2023Applicant: CATALER CORPORATIONInventor: Kosuke MIYAZAKI
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Patent number: 11804555Abstract: The present invention relates to a semiconductor device, wherein the semiconductor substrate includes: a semiconductor layer; and a well region, the semiconductor device includes: a surface electrode provided on a second main surface on a side opposite to a first main surface; a back surface electrode provided on the first main surface; and an upper surface film covering an end edge portion of the surface electrode and at least part of an outer side region outside an end surface of the surface electrode of the semiconductor substrate, the well region includes a portion extending to the outer side region and a portion extending to an inner side region inside the end surface of the surface electrode, and the upper surface film includes at least one outer peripheral opening part provided along an outer periphery of the surface electrode away from the surface electrode of the outer side region.Type: GrantFiled: January 29, 2019Date of Patent: October 31, 2023Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Kohei Ebihara, Shiro Hino, Kosuke Miyazaki, Yasushi Takaki
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Publication number: 20220367613Abstract: A method for manufacturing a semiconductor device includes forming, on first and second impurity layers on a termination region side, an insulating layer, forming a first metal film and a second metal film in this order on the insulating layer and a drift layer, performing dry etching on the first and second metal films all together so that a position of a first end of a metallized layer, which is a remaining part of the first metal film, in the interface region on the termination region side and a position of a second end of an electrode, which is a remaining part of the second metal film, in the interface region on the terminal region side are the same in plan view. The first and second ends are closer to the active region than an end of the second impurity layer on the termination region side in plan view.Type: ApplicationFiled: August 1, 2022Publication date: November 17, 2022Applicant: Mitsubishi Electric CorporationInventors: Yoshinori MATSUNO, Yasushi TAKAKI, Kensuke TAGUCHI, Kosuke MIYAZAKI
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Patent number: 11437465Abstract: A semiconductor device includes an insulating layer provided on a first impurity layer and a second impurity layer on a termination region side, a metallized layer provided on the first impurity layer and the second impurity layer exposed from the insulating layer and on the insulating layer, and an electrode provided on the metallized layer. A position of a first end of the metallized layer on the termination region side and a position of a second end of the electrode on the termination region side are the same in plan view.Type: GrantFiled: April 10, 2020Date of Patent: September 6, 2022Assignee: Mitsubishi Electric CorporationInventors: Yoshinori Matsuno, Yasushi Takaki, Kensuke Taguchi, Kosuke Miyazaki
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Publication number: 20210399144Abstract: The present invention relates to a semiconductor device, wherein the semiconductor substrate includes: a semiconductor layer; and a well region, the semiconductor device includes: a surface electrode provided on a second main surface on a side opposite to a first main surface; a back surface electrode provided on the first main surface; and an upper surface film covering an end edge portion of the surface electrode and at least part of an outer side region outside an end surface of the surface electrode of the semiconductor substrate, the well region includes a portion extending to the outer side region and a portion extending to an inner side region inside the end surface of the surface electrode, and the upper surface film includes at least one outer peripheral opening part provided along an outer periphery of the surface electrode away from the surface electrode of the outer side region.Type: ApplicationFiled: January 29, 2019Publication date: December 23, 2021Applicant: Mitsubishi Electric CorporationInventors: Kohei EBIHARA, Shiro HINO, Kosuke MIYAZAKI, Yasushi TAKAKI
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Publication number: 20200395439Abstract: A semiconductor device includes an insulating layer provided on a first impurity layer and a second impurity layer on a termination region side, a metallized layer provided on the first impurity layer and the second impurity layer exposed from the insulating layer and on the insulating layer, and an electrode provided on the metallized layer. A position of a first end of the metallized layer on the termination region side and a position of a second end of the electrode on the termination region side are the same in plan view.Type: ApplicationFiled: April 10, 2020Publication date: December 17, 2020Applicant: Mitsubishi Electric CorporationInventors: Yoshinori MATSUNO, Yasushi TAKAKI, Kensuke TAGUCHI, Kosuke MIYAZAKI
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Patent number: 9006780Abstract: Between a back surface electrode and an electrode, a first thyristor is formed of fifth and seventh semiconductor regions, a substrate region, first and second semiconductor regions and a third semiconductor region, and a second thyristor is formed of the second and first semiconductor regions, the substrate region, the seventh and fifth semiconductor regions and a sixth semiconductor region. Depths from the surface of the semiconductor substrate to bottom surfaces of the third and fourth semiconductor regions are 20 ?m or more. The second semiconductor region with a high impurity concentration is enclosed by the first semiconductor region with a low impurity concentration, and a difference between a depth from the surface of the semiconductor substrate to the bottom of the second semiconductor region and a depth from the surface of the semiconductor substrate to the bottom of the first semiconductor region is less than 10 ?m.Type: GrantFiled: December 17, 2013Date of Patent: April 14, 2015Assignee: Renesas Electronics CorporationInventors: Aki Moroda, Kosuke Miyazaki
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Publication number: 20140175507Abstract: Between a back surface electrode and an electrode, a first thyristor is formed of fifth and seventh semiconductor regions, a substrate region, first and second semiconductor regions and a third semiconductor region, and a second thyristor is formed of the second and first semiconductor regions, the substrate region, the seventh and fifth semiconductor regions and a sixth semiconductor region. Depths from the surface of the semiconductor substrate to bottom surfaces of the third and fourth semiconductor regions are 20 ?m or more. The second semiconductor region with a high impurity concentration is enclosed by the first semiconductor region with a low impurity concentration, and a difference between a depth from the surface of the semiconductor substrate to the bottom of the second semiconductor region and a depth from the surface of the semiconductor substrate to the bottom of the first semiconductor region is less than 10 ?m.Type: ApplicationFiled: December 17, 2013Publication date: June 26, 2014Applicant: Renesas Electronics CorporationInventors: Aki Moroda, Kosuke Miyazaki
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Patent number: 8242534Abstract: The present invention improves the performance of a semiconductor device formed with a triac. A thyristor is formed between a back surface electrode and an electrode by p-type semiconductor regions, an n-type substrate region, p-type semiconductor regions and an n-type semiconductor region. A thyristor is formed therebetween by the p-type semiconductor regions, the n-type substrate region, the p-type semiconductor regions and an n-type semiconductor region. The two thyristors are opposite in the direction of currents flowing between the back surface electrode and the electrode. The p-type semiconductor region of a high impurity concentration is formed so as to be internally included in the p-type semiconductor region of a low impurity concentration. The p-type semiconductor region of a low impurity concentration is interposed between the p-type semiconductor region of a high impurity concentration and the n-type substrate region.Type: GrantFiled: February 1, 2011Date of Patent: August 14, 2012Assignee: Renesas Electronics CorporationInventors: Aki Moroda, Kosuke Miyazaki
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Publication number: 20110220960Abstract: The present invention improves the performance of a semiconductor device formed with a triac. A thyristor is formed between a back surface electrode and an electrode by p-type semiconductor regions, an n-type substrate region, p-type semiconductor regions and an n-type semiconductor region. A thyristor is formed therebetween by the p-type semiconductor regions, the n-type substrate region, the p-type semiconductor regions and an n-type semiconductor region. The two thyristors are opposite in the direction of currents flowing between the back surface electrode and the electrode. The p-type semiconductor region of a high impurity concentration is formed so as to be internally included in the p-type semiconductor region of a low impurity concentration. The p-type semiconductor region of a low impurity concentration is interposed between the p-type semiconductor region of a high impurity concentration and the n-type substrate region.Type: ApplicationFiled: February 1, 2011Publication date: September 15, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Aki MORODA, Kosuke MIYAZAKI