Patents by Inventor Kosuke Miyazaki

Kosuke Miyazaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11940708
    Abstract: Provided is an optical modulator that can be driven at lower voltage through the use of differential signal output. An optical modulator includes a substrate 1 and optical waveguides (21, 22) and a control electrode that are formed on the substrate, in which the optical waveguide includes Mach-Zehnder type optical waveguide, the control electrode is provided with two ground electrodes sandwiching three signal electrodes; the three signal electrodes are constituted by second and third signal electrodes that sandwich a first signal electrode, and have a wiring structure in which one modulation signal of the differential signal is applied to the first signal electrode, and the other modulation signal of the differential signal is applied to the second and third signal electrodes; and one branched waveguide (21) out of two Mach-Zehnder type optical waveguides is disposed between the first and second signal electrodes, and the other branched waveguide (22) is disposed between the first and third signal electrodes.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: March 26, 2024
    Assignee: SUMITOMO OSAKA CEMENT CO., LTD.
    Inventors: Norikazu Miyazaki, Kosuke Okahashi, Masayuki Motoya
  • Patent number: 11935919
    Abstract: A method for manufacturing a semiconductor device includes forming, on first and second impurity layers on a termination region side, an insulating layer, forming a first metal film and a second metal film in this order on the insulating layer and a drift layer, performing dry etching on the first and second metal films all together so that a position of a first end of a metallized layer, which is a remaining part of the first metal film, in the interface region on the termination region side and a position of a second end of an electrode, which is a remaining part of the second metal film, in the interface region on the terminal region side are the same in plan view. The first and second ends are closer to the active region than an end of the second impurity layer on the termination region side in plan view.
    Type: Grant
    Filed: August 1, 2022
    Date of Patent: March 19, 2024
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yoshinori Matsuno, Yasushi Takaki, Kensuke Taguchi, Kosuke Miyazaki
  • Publication number: 20230420695
    Abstract: A catalyst for fuel cells that contains a carbon powder carrier and catalyst particles carried on the carbon powder carrier, the catalyst particles being Pt alloy particles, the catalyst for fuel cells having 0.65 mmol/g or more of hydrophilic groups, and a Pt elution amount when 0.5 g of the catalyst for fuel cells is immersed in 30 ml of a 0.5 mol/L aqueous sulfuric acid solution and retained for 100 hours at room temperature under stirring being 0.625 mg or less per g of the catalyst for fuel cells.
    Type: Application
    Filed: November 24, 2021
    Publication date: December 28, 2023
    Applicant: CATALER CORPORATION
    Inventor: Kosuke MIYAZAKI
  • Patent number: 11804555
    Abstract: The present invention relates to a semiconductor device, wherein the semiconductor substrate includes: a semiconductor layer; and a well region, the semiconductor device includes: a surface electrode provided on a second main surface on a side opposite to a first main surface; a back surface electrode provided on the first main surface; and an upper surface film covering an end edge portion of the surface electrode and at least part of an outer side region outside an end surface of the surface electrode of the semiconductor substrate, the well region includes a portion extending to the outer side region and a portion extending to an inner side region inside the end surface of the surface electrode, and the upper surface film includes at least one outer peripheral opening part provided along an outer periphery of the surface electrode away from the surface electrode of the outer side region.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: October 31, 2023
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Kohei Ebihara, Shiro Hino, Kosuke Miyazaki, Yasushi Takaki
  • Publication number: 20220367613
    Abstract: A method for manufacturing a semiconductor device includes forming, on first and second impurity layers on a termination region side, an insulating layer, forming a first metal film and a second metal film in this order on the insulating layer and a drift layer, performing dry etching on the first and second metal films all together so that a position of a first end of a metallized layer, which is a remaining part of the first metal film, in the interface region on the termination region side and a position of a second end of an electrode, which is a remaining part of the second metal film, in the interface region on the terminal region side are the same in plan view. The first and second ends are closer to the active region than an end of the second impurity layer on the termination region side in plan view.
    Type: Application
    Filed: August 1, 2022
    Publication date: November 17, 2022
    Applicant: Mitsubishi Electric Corporation
    Inventors: Yoshinori MATSUNO, Yasushi TAKAKI, Kensuke TAGUCHI, Kosuke MIYAZAKI
  • Patent number: 11437465
    Abstract: A semiconductor device includes an insulating layer provided on a first impurity layer and a second impurity layer on a termination region side, a metallized layer provided on the first impurity layer and the second impurity layer exposed from the insulating layer and on the insulating layer, and an electrode provided on the metallized layer. A position of a first end of the metallized layer on the termination region side and a position of a second end of the electrode on the termination region side are the same in plan view.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: September 6, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yoshinori Matsuno, Yasushi Takaki, Kensuke Taguchi, Kosuke Miyazaki
  • Publication number: 20210399144
    Abstract: The present invention relates to a semiconductor device, wherein the semiconductor substrate includes: a semiconductor layer; and a well region, the semiconductor device includes: a surface electrode provided on a second main surface on a side opposite to a first main surface; a back surface electrode provided on the first main surface; and an upper surface film covering an end edge portion of the surface electrode and at least part of an outer side region outside an end surface of the surface electrode of the semiconductor substrate, the well region includes a portion extending to the outer side region and a portion extending to an inner side region inside the end surface of the surface electrode, and the upper surface film includes at least one outer peripheral opening part provided along an outer periphery of the surface electrode away from the surface electrode of the outer side region.
    Type: Application
    Filed: January 29, 2019
    Publication date: December 23, 2021
    Applicant: Mitsubishi Electric Corporation
    Inventors: Kohei EBIHARA, Shiro HINO, Kosuke MIYAZAKI, Yasushi TAKAKI
  • Publication number: 20200395439
    Abstract: A semiconductor device includes an insulating layer provided on a first impurity layer and a second impurity layer on a termination region side, a metallized layer provided on the first impurity layer and the second impurity layer exposed from the insulating layer and on the insulating layer, and an electrode provided on the metallized layer. A position of a first end of the metallized layer on the termination region side and a position of a second end of the electrode on the termination region side are the same in plan view.
    Type: Application
    Filed: April 10, 2020
    Publication date: December 17, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventors: Yoshinori MATSUNO, Yasushi TAKAKI, Kensuke TAGUCHI, Kosuke MIYAZAKI
  • Patent number: 9006780
    Abstract: Between a back surface electrode and an electrode, a first thyristor is formed of fifth and seventh semiconductor regions, a substrate region, first and second semiconductor regions and a third semiconductor region, and a second thyristor is formed of the second and first semiconductor regions, the substrate region, the seventh and fifth semiconductor regions and a sixth semiconductor region. Depths from the surface of the semiconductor substrate to bottom surfaces of the third and fourth semiconductor regions are 20 ?m or more. The second semiconductor region with a high impurity concentration is enclosed by the first semiconductor region with a low impurity concentration, and a difference between a depth from the surface of the semiconductor substrate to the bottom of the second semiconductor region and a depth from the surface of the semiconductor substrate to the bottom of the first semiconductor region is less than 10 ?m.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: April 14, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Aki Moroda, Kosuke Miyazaki
  • Publication number: 20140175507
    Abstract: Between a back surface electrode and an electrode, a first thyristor is formed of fifth and seventh semiconductor regions, a substrate region, first and second semiconductor regions and a third semiconductor region, and a second thyristor is formed of the second and first semiconductor regions, the substrate region, the seventh and fifth semiconductor regions and a sixth semiconductor region. Depths from the surface of the semiconductor substrate to bottom surfaces of the third and fourth semiconductor regions are 20 ?m or more. The second semiconductor region with a high impurity concentration is enclosed by the first semiconductor region with a low impurity concentration, and a difference between a depth from the surface of the semiconductor substrate to the bottom of the second semiconductor region and a depth from the surface of the semiconductor substrate to the bottom of the first semiconductor region is less than 10 ?m.
    Type: Application
    Filed: December 17, 2013
    Publication date: June 26, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Aki Moroda, Kosuke Miyazaki
  • Patent number: 8242534
    Abstract: The present invention improves the performance of a semiconductor device formed with a triac. A thyristor is formed between a back surface electrode and an electrode by p-type semiconductor regions, an n-type substrate region, p-type semiconductor regions and an n-type semiconductor region. A thyristor is formed therebetween by the p-type semiconductor regions, the n-type substrate region, the p-type semiconductor regions and an n-type semiconductor region. The two thyristors are opposite in the direction of currents flowing between the back surface electrode and the electrode. The p-type semiconductor region of a high impurity concentration is formed so as to be internally included in the p-type semiconductor region of a low impurity concentration. The p-type semiconductor region of a low impurity concentration is interposed between the p-type semiconductor region of a high impurity concentration and the n-type substrate region.
    Type: Grant
    Filed: February 1, 2011
    Date of Patent: August 14, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Aki Moroda, Kosuke Miyazaki
  • Publication number: 20110220960
    Abstract: The present invention improves the performance of a semiconductor device formed with a triac. A thyristor is formed between a back surface electrode and an electrode by p-type semiconductor regions, an n-type substrate region, p-type semiconductor regions and an n-type semiconductor region. A thyristor is formed therebetween by the p-type semiconductor regions, the n-type substrate region, the p-type semiconductor regions and an n-type semiconductor region. The two thyristors are opposite in the direction of currents flowing between the back surface electrode and the electrode. The p-type semiconductor region of a high impurity concentration is formed so as to be internally included in the p-type semiconductor region of a low impurity concentration. The p-type semiconductor region of a low impurity concentration is interposed between the p-type semiconductor region of a high impurity concentration and the n-type substrate region.
    Type: Application
    Filed: February 1, 2011
    Publication date: September 15, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Aki MORODA, Kosuke MIYAZAKI