Patents by Inventor Kota NISHIKAWA
Kota NISHIKAWA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11965817Abstract: Disclosed is a cell classification method, to be executed by an analyzer, for classifying cells contained in a specimen, including: preparing a first measurement sample by treating a specimen under a first preparation condition; obtaining a first signal from the prepared first measurement sample; classifying, by using the first signal, cells contained in the first measurement sample; preparing a second measurement sample by treating the specimen under a second preparation condition different from the first preparation condition; obtaining a second signal from the prepared second measurement sample; classifying, by using the second signal, cells contained in the second measurement sample; and comparing a result of the cell classification performed by using the first signal and a result of the cell classification performed by using the second signal, with each other, and outputting an analysis result including a number of cells on the basis of a result of the comparison.Type: GrantFiled: March 4, 2021Date of Patent: April 23, 2024Assignee: SYSMEX CORPORATIONInventors: Yuki Shida, Yukiko Nakamura, Ken Nishikawa, Kota Misawa, Hikaru Onoue, Takaaki Nagai, Masaki Abe, Takahito Mihara, Masaharu Shibata, Konobu Kimura
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Publication number: 20240096422Abstract: A first select transistor is connected to a first wiring. A first memory cell transistor and a second memory cell transistor are connected in series between the first select transistor and a second select transistor. A first word line is connected to the first memory cell transistor. A second word line is connected to the second memory cell transistor. During a first period in which the first voltage is applied to the first wiring, a second voltage lower than a first voltage is applied in parallel to the first word line and the second word line. During a second period in which a third voltage higher than the first voltage is applied to the first wiring, the second voltage is applied to the first word line, and a fourth voltage higher than the second voltage and lower than the third voltage is applied to the second word line.Type: ApplicationFiled: September 1, 2023Publication date: March 21, 2024Applicant: Kioxia CorporationInventors: Hiroaki KOSAKO, Kota NISHIKAWA, Kenrou KIKUCHI
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Patent number: 11881267Abstract: A semiconductor memory device includes a substrate, gate electrodes, a semiconductor layer opposed to gate electrodes, an electric charge accumulating layer disposed between gate electrodes and the semiconductor layer, a conductive layer connected to one end portion of the semiconductor layer, and a control circuit electrically connected to gate electrodes and the conductive layer. Gate electrodes include first gate electrodes, second gate electrodes, and third gate electrode. The control circuit is configured to perform an erase operation. The erase operation includes: at least one-time first operation that applies a first voltage to the conductive layer; a second operation performed after the first operation, the second operation applying a second voltage to the third gate electrode; and at least one-time third operation performed after the second operation, the third operation applying a third voltage same as or larger than the first voltage to the conductive layer.Type: GrantFiled: March 9, 2022Date of Patent: January 23, 2024Assignee: KIOXIA CORPORATIONInventors: Manabu Sakaniwa, Yasuhiro Shiino, Kota Nishikawa, Yu Ishiyama, Shinji Suzuki
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Publication number: 20230056364Abstract: A semiconductor memory device includes a substrate, gate electrodes, a semiconductor layer opposed to gate electrodes, an electric charge accumulating layer disposed between gate electrodes and the semiconductor layer, a conductive layer connected to one end portion of the semiconductor layer, and a control circuit electrically connected to gate electrodes and the conductive layer. Gate electrodes include first gate electrodes, second gate electrodes, and third gate electrode. The control circuit is configured to perform an erase operation. The erase operation includes: at least one-time first operation that applies a first voltage to the conductive layer; a second operation performed after the first operation, the second operation applying a second voltage to the third gate electrode; and at least one-time third operation performed after the second operation, the third operation applying a third voltage same as or larger than the first voltage to the conductive layer.Type: ApplicationFiled: March 9, 2022Publication date: February 23, 2023Applicant: KIOXIA CORPORATIONInventors: Manabu SAKANIWA, Yasuhiro SHIINO, Kota NISHIKAWA, Yu ISHIYAMA, Shinji SUZUKI
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Patent number: 10998337Abstract: According to one embodiment, a semiconductor memory device includes the following configuration. A second word line is provided above a first word line on a substrate. A third word line is provided above the second word line. A semiconductor layer includes a first part that passes through the first word line, a second part that passes through the second and the third word lines, and is provided above the first part, and a joint provided between the first and second parts. When a write operation is performed on a memory cell of the third word line, prior to applying a write voltage to the third word line, a first voltage is applied to a bit line, a second voltage is applied to the third word line, and a third voltage higher than the second voltage is applied to the second word line.Type: GrantFiled: August 13, 2020Date of Patent: May 4, 2021Assignee: Toshiba Memory CorporationInventors: Kota Nishikawa, Hiroshi Tsubouchi, Kenri Nakai
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Publication number: 20200373326Abstract: According to one embodiment, a semiconductor memory device includes the following configuration. A second word line is provided above a first word line on a substrate. A third word line is provided above the second word line. A semiconductor layer includes a first part that passes through the first word line, a second part that passes through the second and the third word lines, and is provided above the first part, and a joint provided between the first and second parts. When a write operation is performed on a memory cell of the third word line, prior to applying a write voltage to the third word line, a first voltage is applied to a bit line, a second voltage is applied to the third word line, and a third voltage higher than the second voltage is applied to the second word line.Type: ApplicationFiled: August 13, 2020Publication date: November 26, 2020Applicant: Toshiba Memory CorporationInventors: Kota NISHIKAWA, Hiroshi TSUBOUCHI, Kenri NAKAI
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Patent number: 10748926Abstract: According to one embodiment, a semiconductor memory device includes the following configuration. A second word line is provided above a first word line on a substrate. A third word line is provided above the second word line. A semiconductor layer includes a first part that passes through the first word line, a second part that passes through the second and the third word lines, and is provided above the first part, and a joint provided between the first and second parts. When a write operation is performed on a memory cell of the third word line, prior to applying a write voltage to the third word line, a first voltage is applied to a bit line, a second voltage is applied to the third word line, and a third voltage higher than the second voltage is applied to the second word line.Type: GrantFiled: March 12, 2019Date of Patent: August 18, 2020Assignee: Toshiba Memory CorporationInventors: Kota Nishikawa, Hiroshi Tsubouchi, Kenri Nakai
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Publication number: 20200006379Abstract: According to one embodiment, a semiconductor memory device includes the following configuration. A second word line is provided above a first word line on a substrate. A third word line is provided above the second word line. A semiconductor layer includes a first part that passes through the first word line, a second part that passes through the second and the third word lines, and is provided above the first part, and a joint provided between the first and second parts. When a write operation is performed on a memory cell of the third word line, prior to applying a write voltage to the third word line, a first voltage is applied to a bit line, a second voltage is applied to the third word line, and a third voltage higher than the second voltage is applied to the second word line.Type: ApplicationFiled: March 12, 2019Publication date: January 2, 2020Applicant: Toshiba Memory CorporationInventors: Kota NISHIKAWA, Hiroshi TSUBOUCHI, Kenri NAKAI
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Patent number: 9318207Abstract: A nonvolatile semiconductor memory device according to an embodiment comprises a control unit, during a data erase, applying at least to a word line connected to a memory cell disposed most to a source line side a lower control voltage than that applied to a word line connected to a memory cell disposed most to a bit line side, of a plurality of word lines connected to at least a plurality of memory cells mutually written with data of an identical number of bits in a cell string.Type: GrantFiled: December 15, 2014Date of Patent: April 19, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Kota Nishikawa, Masanori Hatakeyama, Takanori Eto, Atsuhiro Suzuki
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Publication number: 20160049199Abstract: A nonvolatile semiconductor memory device according to an embodiment comprises a control unit, during a data erase, applying at least to a word line connected to a memory cell disposed most to a source line side a lower control voltage than that applied to a word line connected to a memory cell disposed most to a bit line side, of a plurality of word lines connected to at least a plurality of memory cells mutually written with data of an identical number of bits in a cell string.Type: ApplicationFiled: December 15, 2014Publication date: February 18, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Kota NISHIKAWA, Masanori Hatakeyama, Takanori Eto, Atsuhiro Suzuki