Patents by Inventor Kotaro Mizuno
Kotaro Mizuno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12260995Abstract: A ceramic electronic device includes a multilayer chip in which dielectric layers and internal electrode layers each including Ni as a main phase are alternately stacked. At least one of the dielectric layers includes Si. One of the internal electrode layers next to the at least one of the dielectric layers includes a layer including an additive element including one or more of Au, Pt, Cu, Fe, Cr, Zn, and In. A peak of a concentration of the additive element and/or a peak of a concentration of Si in the one of the internal electrode layers and the at least one of the dielectric layers exist(s) in a region within 15 nm in a thickness direction from an interface between the one of the internal electrode layers and the at least one of the dielectric layers.Type: GrantFiled: April 29, 2024Date of Patent: March 25, 2025Assignee: TAIYO YUDEN CO., LTD.Inventor: Kotaro Mizuno
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Patent number: 12243691Abstract: A ceramic electronic device includes a multilayer chip in which dielectric layers and internal electrode layers are alternately stacked. In an outermost one of the internal electrode layers, a metal oxide containing a main component element constituting the internal electrode layers is provided on an outer main surface of the outermost one, and a formation depth of the metal oxide is 0.5 ?m or more and 5.0 ?m or less. A segregation layer containing a sub metal element different from the main component metal is present at an interface between at least one of the internal electrode layers other than the outermost one and one of the dielectric layers adjacent to the at least one of the internal electrode layers.Type: GrantFiled: February 24, 2023Date of Patent: March 4, 2025Assignee: TAIYO YUDEN CO., LTD.Inventor: Kotaro Mizuno
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Publication number: 20250069813Abstract: A multi-layer ceramic capacitor includes: a multi-layer unit including ceramic layers laminated in a first direction and electrodes disposed between the ceramic layers, positions of end portions of the electrodes falling within a range of 0.5 ?m in a second direction; and side margins each containing manganese or magnesium and silicon and facing each other in the second direction. When each margin is equally divided into an inner region and an outer region, a total concentration of manganese and magnesium in the outer region is higher than a total concentration of manganese and magnesium in the inner region and higher than a total concentration of manganese and magnesium in the ceramic layers, and a concentration of silicon in the inner region is not less than a concentration of silicon in the outer region and higher than a concentration of silicon in the ceramic layers.Type: ApplicationFiled: November 13, 2024Publication date: February 27, 2025Applicant: TAIYO YUDEN CO., LTD.Inventor: Kotaro MIZUNO
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Patent number: 12230764Abstract: An all solid battery includes: a solid electrolyte layer of which a main component is oxide-based solid electrolyte; a first electrode layer that is provided on a first main face of the solid electrolyte layer and includes an active material; and a second electrode layer that is provided on a second main face of the solid electrolyte layer and includes an active material, wherein at least one of the first electrode layer and the second electrode layer includes an aggregate of carbon particles and a cavity, wherein the aggregate demarcates at least a part of the cavity.Type: GrantFiled: June 11, 2020Date of Patent: February 18, 2025Assignee: TAIYO YUDEN CO., LTD.Inventors: Sachie Tomizawa, Daigo Ito, Chie Kawamura, Kotaro Mizuno
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Publication number: 20250002416Abstract: Provided is a laminated ceramic capacitor having a capacitance less reduced by a sintering agent. A laminated ceramic capacitor according to one aspect of the invention includes a body having a first internal electrode layer, a second internal electrode layer, and a ceramic layer disposed therebetween. The ceramic layer is formed from ceramic material containing a sintering agent composed mainly of a sintering agent element. The first internal electrode layer includes an electrode part and a non-electrode part, the electrode part being formed of a sintered compact of a main component metal element, the non-electrode part being surrounded by the electrode part. The non-electrode part contains the sintering agent element. A first concentration indicating a concentration of the sintering agent element in the non-electrode part is higher than a second concentration indicating the same in an interface between the first internal electrode layer and the ceramic layer.Type: ApplicationFiled: June 14, 2024Publication date: January 2, 2025Inventor: Kotaro MIZUNO
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Patent number: 12170175Abstract: A multi-layer ceramic capacitor includes: a multi-layer unit including ceramic layers laminated in a first direction and electrodes disposed between the ceramic layers, positions of end portions of the electrodes falling within a range of 0.5 ?m in a second direction; and side margins each containing manganese or magnesium and silicon and facing each other in the second direction. When each margin is equally divided into an inner region and an outer region, a total concentration of manganese and magnesium in the outer region is higher than a total concentration of manganese and magnesium in the inner region and higher than a total concentration of manganese and magnesium in the ceramic layers, and a concentration of silicon in the inner region is not less than a concentration of silicon in the outer region and higher than a concentration of silicon in the ceramic layers.Type: GrantFiled: July 25, 2023Date of Patent: December 17, 2024Assignee: TAIYO YUDEN CO., LTD.Inventor: Kotaro Mizuno
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Publication number: 20240290545Abstract: A ceramic electronic device includes a multilayer chip in which dielectric layers and internal electrode layers each including Ni as a main phase are alternately stacked. At least one of the dielectric layers includes Si. One of the internal electrode layers next to the at least one of the dielectric layers includes a layer including an additive element including one or more of Au, Pt, Cu, Fe, Cr, Zn, and In. A peak of a concentration of the additive element and/or a peak of a concentration of Si in the one of the internal electrode layers and the at least one of the dielectric layers exist(s) in a region within 15 nm in a thickness direction from an interface between the one of the internal electrode layers and the at least one of the dielectric layers.Type: ApplicationFiled: April 29, 2024Publication date: August 29, 2024Inventor: Kotaro MIZUNO
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Patent number: 12073996Abstract: A ceramic electronic device includes a multilayer chip in which each of a plurality of dielectric layers of which a main component is ceramic, and each of a plurality of internal electrode layers are alternately stacked. The plurality of internal electrode layers include Ni, S and Sn.Type: GrantFiled: February 23, 2022Date of Patent: August 27, 2024Assignee: TAIYO YUDEN CO., LTD.Inventor: Kotaro Mizuno
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Patent number: 12002630Abstract: A ceramic electronic device includes a multilayer chip in which each of a plurality of dielectric layers and each of a plurality of internal electrode layers including Ni as a main phase are alternately stacked. At least one of the plurality of dielectric layers includes a secondary phase including Si, at an interface between the at least one of the plurality of dielectric layers and one of the plurality of internal electrode layers next to the at least one of the plurality of dielectric layers. The one of the plurality of internal electrode layers includes a layer including an additive element including one or more of Au, Pt, Cu, Fe, Cr, Zn, and In, at a region contacting the secondary phase at the interface.Type: GrantFiled: September 7, 2022Date of Patent: June 4, 2024Assignee: TAIYO YUDEN CO., LTD.Inventor: Kotaro Mizuno
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Publication number: 20240112861Abstract: A ceramic electronic component contains a multilayer chip constituted by alternately stacked multiple dielectric layers whose primary component is ceramic, and multiple internal electrode layers whose primary component is metal, wherein: at least one of the multiple internal electrode layers has, at its interface with an adjoining dielectric layer, a segregation layer containing an additive metal element(s) different from the primary component metal of the internal electrode layers; Si and the additive metal element(s) are present at least at one grain boundary in the adjoining dielectric layer; and the atomic concentration ratio of the additive metal element(s)/Si at the grain boundary is 1.3 or higher.Type: ApplicationFiled: September 21, 2023Publication date: April 4, 2024Inventor: Kotaro MIZUNO
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Patent number: 11948753Abstract: A manufacturing method of a multilayer ceramic electronic device includes: forming each of stack units by forming each of internal electrode patterns on each of dielectric green sheets, the each of internal electrode patterns including Ni, Sn and Au; forming a multilayer structure by stacking the each of stack units; and firing the multilayer structure, whereby each internal electrode layer is formed from the each of internal electrode patterns and each dielectric layer is formed from the each of the dielectric green sheets wherein, in the each internal electrode layer, an Au concentration near each interface between the each internal electrode layer and the each dielectric layer is larger than an Au concentration in each center portion in a thickness direction.Type: GrantFiled: June 1, 2023Date of Patent: April 2, 2024Assignee: TAIYO YUDEN CO., LTD.Inventors: Kazuki Yamada, Kotaro Mizuno, Yoichi Kato, Hidetoshi Masuda
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Patent number: 11915882Abstract: A ceramic electronic device includes a multilayer chip in which a dielectric layer and an internal electrode layer are alternately stacked. Concentration peaks of two or more types of metals different from a main component metal of the internal electrode layer exist at different positions in a stacking direction of the dielectric layer and the internal electrode layer, between the dielectric layer and the internal electrode layer.Type: GrantFiled: August 30, 2022Date of Patent: February 27, 2024Assignee: TAIYO YUDEN CO., LTD.Inventors: Hidetoshi Masuda, Kotaro Mizuno, Koichi Tsukagoshi
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Publication number: 20230377805Abstract: A multi-layer ceramic capacitor includes: a multi-layer unit including ceramic layers laminated in a first direction and electrodes disposed between the ceramic layers, positions of end portions of the electrodes falling within a range of 0.5 ?m in a second direction; and side margins each containing manganese or magnesium and silicon and facing each other in the second direction. When each margin is equally divided into an inner region and an outer region, a total concentration of manganese and magnesium in the outer region is higher than a total concentration of manganese and magnesium in the inner region and higher than a total concentration of manganese and magnesium in the ceramic layers, and a concentration of silicon in the inner region is not less than a concentration of silicon in the outer region and higher than a concentration of silicon in the ceramic layers.Type: ApplicationFiled: July 25, 2023Publication date: November 23, 2023Applicant: TAIYO YUDEN CO., LTD.Inventor: Kotaro MIZUNO
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Publication number: 20230367120Abstract: A vehicle display apparatus includes: an image display device that includes a display surface that displays an image; a lens member that is arranged facing the display surface; and an optical system that includes a mirror and forms, using the mirror, an optical path from the lens member to a reflection surface on a windshield. The lens member includes an incident surface that faces the display surface and an emission surface that emits display light of the image toward the mirror. When viewed from an image horizontal direction, the lens member is tapered with a thickness from the incident surface to the emission surface being reduced toward one side in an image vertical direction. When viewed from the image horizontal direction, the display surface is inclined relative to a direction orthogonal to the optical path of the display light emitted from the emission surface to the mirror.Type: ApplicationFiled: April 14, 2023Publication date: November 16, 2023Inventors: Naohisa Murata, Kotaro Mizuno, Takuya Ishigami
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Publication number: 20230326680Abstract: A manufacturing method of a multilayer ceramic electronic device includes: forming each of stack units by forming each of internal electrode patterns on each of dielectric green sheets, the each of internal electrode patterns including Ni, Sn and Au; forming a multilayer structure by stacking the each of stack units; and firing the multilayer structure, whereby each internal electrode layer is formed from the each of internal electrode patterns and each dielectric layer is formed from the each of the dielectric green sheets wherein, in the each internal electrode layer, an Au concentration near each interface between the each internal electrode layer and the each dielectric layer is larger than an Au concentration in each center portion in a thickness direction.Type: ApplicationFiled: June 1, 2023Publication date: October 12, 2023Inventors: Kazuki YAMADA, Kotaro MIZUNO, Yoichi KATO, Hidetoshi MASUDA
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Publication number: 20230290576Abstract: A ceramic electronic device includes a multilayer chip in which dielectric layers and internal electrode layers are alternately stacked. In an outermost one of the internal electrode layers, a metal oxide containing a main component element constituting the internal electrode layers is provided on an outer main surface of the outermost one, and a formation depth of the metal oxide is 0.5 ?m or more and 5.0 ?m or less. A segregation layer containing a sub metal element different from the main component metal is present at an interface between at least one of the internal electrode layers other than the outermost one and one of the dielectric layers adjacent to the at least one of the internal electrode layers.Type: ApplicationFiled: February 24, 2023Publication date: September 14, 2023Inventor: Kotaro MIZUNO
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Patent number: 11756737Abstract: A multi-layer ceramic capacitor includes: a multi-layer unit including ceramic layers laminated in a first direction and electrodes disposed between the ceramic layers, positions of end portions of the electrodes falling within a range of 0.5 ?m in a second direction; and side margins each containing manganese or magnesium and silicon and facing each other in the second direction. When each margin is equally divided into an inner region and an outer region, a total concentration of manganese and magnesium in the outer region is higher than a total concentration of manganese and magnesium in the inner region and higher than a total concentration of manganese and magnesium in the ceramic layers, and a concentration of silicon in the inner region is not less than a concentration of silicon in the outer region and higher than a concentration of silicon in the ceramic layers.Type: GrantFiled: January 31, 2022Date of Patent: September 12, 2023Assignee: TAIYO YUDEN CO., LTD.Inventor: Kotaro Mizuno
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Patent number: 11710601Abstract: A ceramic electronic device includes a multilayer chip in which a plurality of dielectric layers of which a main component is ceramic and a plurality of internal electrode layers are stacked. The plurality of internal electrode layers include Ni, Sn and Au.Type: GrantFiled: July 9, 2021Date of Patent: July 25, 2023Assignee: TAIYO YUDEN CO., LTD.Inventors: Kazuki Yamada, Kotaro Mizuno, Yoichi Kato, Hidetoshi Masuda
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Patent number: 11677098Abstract: An all solid battery includes a multilayer chip in which each of a plurality of solid electrolyte layers including solid electrolyte and each of a plurality of internal electrodes including an electrode active material are alternately stacked, the multilayer chip having a rectangular parallelepiped shape, the plurality of internal electrodes being alternately exposed to two side faces of the multilayer chip other than two end faces of a stacking direction of the multilayer chip, and a pair of external electrodes that contacts the two side faces and include solid electrolyte.Type: GrantFiled: December 1, 2020Date of Patent: June 13, 2023Assignee: TAIYO YUDEN CO., LTD.Inventors: Daigo Ito, Kotaro Mizuno
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Patent number: 11626615Abstract: An all solid battery includes a multilayer chip in which each of a plurality of solid electrolyte layers including solid electrolyte and each of a plurality of internal electrodes including an electrode active material are alternately stacked, the multilayer chip having a rectangular parallelepiped shape, the plurality of internal electrodes being alternately exposed to two side faces of the multilayer chip other than two end faces of a stacking direction of the multilayer chip, and a pair of external electrodes that contacts the two side faces. At least one of the pair of external electrodes includes an electrode active material of which a pole is a same as that of an electrode active material of the internal electrode which contacts the one of the pair of external electrodes.Type: GrantFiled: December 2, 2020Date of Patent: April 11, 2023Assignee: TAIYO YUDEN CO., LTD.Inventors: Daigo Ito, Kotaro Mizuno