Patents by Inventor Kotaro Noda

Kotaro Noda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9711526
    Abstract: According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, and a columnar part. The stacked body is provided on the substrate. The stacked body includes a plurality of first insulating films and a plurality of electrode films alternately stacked one layer by one layer. The columnar part includes a semiconductor pillar provided in the stacked body and extending in a stacking direction of the stacked body, and a memory film provided between the semiconductor pillar and the stacked body. The electrode films include a first portion provided on a side part of the columnar part, a second part contacting the first portion and provided further outside the columnar part, and a first conductive layer covering an upper surface and a lower surface of the first portion.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: July 18, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kotaro Noda, Natsuki Kikuchi, Masaru Kito
  • Patent number: 9711527
    Abstract: According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a semiconductor pillar, a charge storage film, and at least one columnar member. The stacked body is provided on the substrate. In the stacked body, a plurality of insulating films and a plurality of electrode films are layered together alternately. The semiconductor pillar is provided in the stacked body and extends in a stacking direction of the stacked body. The charge storage film is provided between the semiconductor pillar and the stacked body. The columnar member is provided in the stacked body and extends in the stacking direction. A lower portion of the columnar member is provided in the substrate.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: July 18, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kotaro Noda, Kyoko Noda, Aya Minemura, Kenji Sawamura
  • Publication number: 20170179147
    Abstract: A semiconductor memory device according to an embodiment comprises: when three directions intersecting each other are assumed to be first through third directions, and two directions intersecting each other in a plane extending in the first and second directions are assumed to be fourth and fifth directions, a memory cell array including: a conductive layer stacked in the third direction above a semiconductor substrate and having a first region; and a first columnar body penetrating the first region of the conductive layer in the third direction and including a semiconductor film, the first columnar body having a cross-section along the first and second directions in which, at a first position which is a certain position in the third direction, a length in the fourth direction is shorter than a length in the fifth direction.
    Type: Application
    Filed: March 8, 2017
    Publication date: June 22, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Kotaro NODA
  • Publication number: 20170148806
    Abstract: According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, and a columnar part. The stacked body is provided on the substrate. The stacked body includes a plurality of first insulating films and a plurality of electrode films alternately stacked one layer by one layer. The columnar part includes a semiconductor pillar provided in the stacked body and extending in a stacking direction of the stacked body, and a memory film provided between the semiconductor pillar and the stacked body. The electrode films include a first portion provided on a side part of the columnar part, a second part contacting the first portion and provided further outside the columnar part, and a first conductive layer covering an upper surface and a lower surface of the first portion.
    Type: Application
    Filed: February 19, 2016
    Publication date: May 25, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kotaro NODA, Natsuki KIKUCHI, Masaru KITO
  • Publication number: 20170110659
    Abstract: According to one embodiment, a semiconductor memory device includes a plurality of first interconnects extending in a first direction, a plurality of second interconnects extending in a second direction, a plurality of stacked films respectively provided between the first interconnects and the second interconnects, each of the plurality of stacked films including a variable resistance film, a first inter-layer insulating film provided in a first region between the stacked films, and a second inter-layer insulating film provided in a second region having a wider width than the first region. The second inter-layer insulating film includes a plurality of protrusions configured to support one portion of the plurality of second interconnects on the second region. A protruding length of the protrusions is less than a stacking height of the stacked films.
    Type: Application
    Filed: December 28, 2016
    Publication date: April 20, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Kotaro NODA
  • Patent number: 9613896
    Abstract: A semiconductor memory device according to an embodiment comprises: when three directions intersecting each other are assumed to be first through third directions, and two directions intersecting each other in a plane extending in the first and second directions are assumed to be fourth and fifth directions, a memory cell array including: a conductive layer stacked in the third direction above a semiconductor substrate and having a first region; and a first columnar body penetrating the first region of the conductive layer in the third direction and including a semiconductor film, the first columnar body having a cross-section along the first and second directions in which, at a first position which is a certain position in the third direction, a length in the fourth direction is shorter than a length in the fifth direction.
    Type: Grant
    Filed: June 4, 2015
    Date of Patent: April 4, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Kotaro Noda
  • Publication number: 20170077127
    Abstract: According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a semiconductor pillar, a charge storage film, and at least one columnar member. The stacked body is provided on the substrate. In the stacked body, a plurality of insulating films and a plurality of electrode films are layered together alternately. The semiconductor pillar is provided in the stacked body and extends in a stacking direction of the stacked body. The charge storage film is provided between the semiconductor pillar and the stacked body. The columnar member is provided in the stacked body and extends in the stacking direction. A lower portion of the columnar member is provided in the substrate.
    Type: Application
    Filed: February 19, 2016
    Publication date: March 16, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kotaro NODA, Kyoko Noda, Aya Minemura, Kenji Sawamura
  • Patent number: 9583538
    Abstract: According to one embodiment, a semiconductor memory device includes a plurality of first interconnects extending in a first direction, a plurality of second interconnects extending in a second direction, a plurality of stacked films respectively provided between the first interconnects and the second interconnects, each of the plurality of stacked films including a variable resistance film, a first inter-layer insulating film provided in a first region between the stacked films, and a second inter-layer insulating film provided in a second region having a wider width than the first region. The second inter-layer insulating film includes a plurality of protrusions configured to support one portion of the plurality of second interconnects on the second region. A protruding length of the protrusions is less than a stacking height of the stacked films.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: February 28, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kotaro Noda
  • Patent number: 9484298
    Abstract: A non-volatile memory device includes a first electrode layer extending in a first direction and a first channel body extending through the first electrode layer in a second direction. The first electrode layer has, on a side surface, a first projecting portion expanding in a third direction perpendicular to the first direction and the second direction, and having a rounding shape in a tip of the first projecting portion.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: November 1, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kotaro Noda, Tomohiro Yamada
  • Patent number: 9455269
    Abstract: A semiconductor memory device according to an embodiment comprises: a memory cell array, the memory cell array including: a conductive layer, an inter-layer insulating layer, and a conductive line stacked on a semiconductor substrate in a stacking direction; first and second connecting lines that contact the semiconductor substrate and are electrically connected to the conductive line and that extend in the stacking direction; and a columnar body that penetrates the conductive layer and the inter-layer insulating layer in the stacking direction between the first and second connecting lines and that includes a first semiconductor layer, the semiconductor substrate having: a first impurity region to which a first impurity is added at a place of contact with the first connecting line; and a second impurity region to which a second impurity different from the first impurity is added at a place of contact with the second connecting line.
    Type: Grant
    Filed: June 10, 2015
    Date of Patent: September 27, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Kotaro Noda
  • Publication number: 20160276362
    Abstract: A semiconductor memory device according to an embodiment comprises: a memory cell array, the memory cell array including: a conductive layer, an inter-layer insulating layer, and a conductive line stacked on a semiconductor substrate in a stacking direction; first and second connecting lines that contact the semiconductor substrate and are electrically connected to the conductive line and that extend in the stacking direction; and a columnar body that penetrates the conductive layer and the inter-layer insulating layer in the stacking direction between the first and second connecting lines and that includes a first semiconductor layer, the semiconductor substrate having: a first impurity region to which a first impurity is added at a place of contact with the first connecting line; and a second impurity region to which a second impurity different from the first impurity is added at a place of contact with the second connecting line.
    Type: Application
    Filed: June 10, 2015
    Publication date: September 22, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Kotaro NODA
  • Publication number: 20160276361
    Abstract: A semiconductor memory device according to an embodiment comprises: conductive layers stacked in a vertical direction on a semiconductor substrate; and first and columnar bodies that extend in the vertical direction, the first and second columnar bodies each comprising: a first film; a second film disposed on the first film; and a semiconductor film, and the first film of the second columnar body having an upper end positioned higher than a first position lower than a first conductive layer and lower than a second position higher than the first conductive layer and a lower end positioned at or lower than the first position, and the second film of the second columnar body having an upper end positioned higher than the second position and a lower end positioned lower than the first position.
    Type: Application
    Filed: June 5, 2015
    Publication date: September 22, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Kotaro NODA
  • Publication number: 20160276264
    Abstract: A semiconductor memory device according to an embodiment comprises: when three directions intersecting each other are assumed to be first through third directions, and two directions intersecting each other in a plane extending in the first and second directions are assumed to be fourth and fifth directions, a memory cell array including: a conductive layer stacked in the third direction above a semiconductor substrate and having a first region; and a first columnar body penetrating the first region of the conductive layer in the third direction and including a semiconductor film, the first columnar body having a cross-section along the first and second directions in which, at a first position which is a certain position in the third direction, a length in the fourth direction is shorter than a length in the fifth direction.
    Type: Application
    Filed: June 4, 2015
    Publication date: September 22, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Kotaro NODA
  • Publication number: 20160268266
    Abstract: A semiconductor memory device according to an embodiment comprises: a memory cell array, the memory cell array including: an inter-layer insulating layer and a conductive layer stacked in a stacking direction; a columnar semiconductor layer having a side surface that faces side surfaces of the inter-layer insulating layer and the conductive layer and extending in the stacking direction; and a block insulating layer and a block high-permittivity layer disposed between the columnar semiconductor layer and the conductive layer, the block insulating layer including: a first block insulating film that covers a side surface of the columnar semiconductor layer from a lower surface of the inter-layer insulating layer to an upper surface of the conductive layer in the stacking direction; and a second block insulating film that contacts the first block insulating film and covers at least a side surface and a lower surface of the conductive layer.
    Type: Application
    Filed: June 3, 2015
    Publication date: September 15, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kotaro NODA, Kyoko NODA
  • Publication number: 20160268289
    Abstract: According to one embodiment, an integrated circuit device includes a pillar extending in a first direction and a plug that is connected to an end part of the pillar on a longitudinal direction side. A contact face between the pillar and the plug including a portion inclined relative to a plane perpendicular to the first direction.
    Type: Application
    Filed: March 13, 2015
    Publication date: September 15, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Kotaro NODA
  • Patent number: 9401332
    Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The method can include forming a stacked layer in a memory cell region and a mark region, forming a first mask layer above the stacked layer, and forming a second mask layer above the first mask layer; forming the second mask layer into first mask pattern features and forming a first alignment mark pattern feature; forming second mask pattern features and then removing the first mask pattern features; opening part of the second mask pattern features and forming a third mask layer having an opening; removing part of the second mask pattern features; removing the third mask layer; forming a fourth mask layer; etching the first mask layer; removing the fourth mask layer and then removing the second mask pattern features; and etching the stacked layer.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: July 26, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kotaro Noda
  • Publication number: 20160079365
    Abstract: According one embodiment, a memory device includes: a stacked body provided on a foundation layer, the stacked body including electrode layers stacked alternately with first insulating layers, at least one of the plurality of electrode layers including a first portion and a second portion, a first length between the first portion and the foundation layer being longer than a second length between the second portion and the foundation layer, difference between the first length and the second length increasing toward the foundation layer; a semiconductor member piercing the second portion, the semiconductor member extending in a direction of the stacking of the electrode layers and the first insulating layers, the semiconductor member including a region where maximum length of the semiconductor member cut perpendicularly to the direction decreases toward the foundation layer; and a memory film provided between the semiconductor member and each of the electrode layers.
    Type: Application
    Filed: March 4, 2015
    Publication date: March 17, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Kotaro NODA
  • Publication number: 20160071864
    Abstract: According to one embodiment, a semiconductor memory device includes a stacked body which is provided on a substrate and in which an insulating film and an electrode film are alternately stacked. The semiconductor memory device also includes an insulating member which penetrates the stacked body in a stacking direction of the insulating film and the electrode film to thereby separate the stacked body. The semiconductor memory device also includes a semiconductor pillar which penetrates the stacked body in the stacking direction. A maximum portion of the insulating member where a first distance from a side surface of the insulating member to a central plane of the insulating member becomes maximum and a maximum portion of the semiconductor pillar where a second distance from a side surface of the semiconductor pillar to a center line of the semiconductor pillar becomes maximum being provided in different positions in the stacking direction.
    Type: Application
    Filed: March 12, 2015
    Publication date: March 10, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Kotaro NODA
  • Publication number: 20160071874
    Abstract: According to one embodiment, an integrated circuit device includes a substrate. The integrated circuit device also includes a stacked body provided on the substrate, insulating films and electrode films being alternately stacked in the stacked body. The integrated circuit device also includes a stopper member selectively provided in the electrode film in a bottom layer and a first stopper protection film provided on a side surface of the stopper member. The integrated circuit device also includes an insulating member provided immediately on the stopper member and configured to pierce through the stacked body in a stacking direction of the insulating films and the electrode films, a lower end of the insulating member disposed in the stopper member. The integrated circuit device also includes a semiconductor pillar provided in a side direction of the insulating member and configured to pierce through the stacked body in the stacking direction.
    Type: Application
    Filed: March 12, 2015
    Publication date: March 10, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Kotaro NODA
  • Publication number: 20160064667
    Abstract: A semiconductor memory device according to an embodiment has a memory cell array including: a plurality of lower wirings extending in the first direction; a plurality of upper wirings extending in the second direction, the upper wirings placed above the plurality of lower wirings; a plurality of memory cells provided at respective crossings of the plurality of lower wirings and the plurality of upper wirings; and an interlayer insulating film provided between the plurality of memory cells adjacent in the second direction, and the device is characterized in that the upper wiring includes: an upper firing first section deposited on the memory cell; and an upper wiring second section deposited on the interlayer insulating film, the upper wiring second section larger in crystal grain size than the upper wiring first section, and an upper surface of the memory cell is lower than an upper surface of the interlayer insulating film.
    Type: Application
    Filed: November 9, 2015
    Publication date: March 3, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Kotaro NODA