Patents by Inventor Kotoku Sato
Kotoku Sato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8619487Abstract: A semiconductor device includes a memory core with a plurality of memory cells, an internal voltage generator and a low power entry circuit. The low power entry circuit receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited. The internal voltage generator includes a detector and at least one of booster circuits. The internal voltage generator, coupled to the memory core via an internal power supply line, generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line. The internal voltage generator stops supplying the boosted internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device.Type: GrantFiled: January 23, 2012Date of Patent: December 31, 2013Assignee: Fujitsu Semiconductor LimitedInventors: Shinya Fujioka, Tomohiro Kawakubo, Koichi Nishimura, Kotoku Sato
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Publication number: 20130332761Abstract: A semiconductor device includes a memory core with a plurality of memory cells, an internal voltage generator and a low power entry circuit. The low power entry circuit receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited. The internal voltage generator includes a detector and at least one of booster circuits. The internal voltage generator, coupled to the memory core via an internal power supply line, generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line. The internal voltage generator stops supplying the boosted internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device.Type: ApplicationFiled: August 6, 2013Publication date: December 12, 2013Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Shinya FUJIOKA, Tomohiro Kawakubo, Koichi Nishimura, Kotoku Sato
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Publication number: 20130326246Abstract: A semiconductor device includes a memory core with a plurality of memory cells, an internal voltage generator and a low power entry circuit. The low power entry circuit receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited. The internal voltage generator includes a detector and at least one of booster circuits. The internal voltage generator, coupled to the memory core via an internal power supply line, generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line. The internal voltage generator stops supplying the boosted internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device.Type: ApplicationFiled: August 6, 2013Publication date: December 5, 2013Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Shinya FUJIOKA, Tomohiro Kawakubo, Koichi Nishimura, Kotoku Sato
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Publication number: 20130322198Abstract: A semiconductor device includes a memory core with a plurality of memory cells, an internal voltage generator and a low power entry circuit. The low power entry circuit receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited. The internal voltage generator includes a detector and at least one of booster circuits. The internal voltage generator, coupled to the memory core via an internal power supply line, generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line. The internal voltage generator stops supplying the boosted internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device.Type: ApplicationFiled: August 6, 2013Publication date: December 5, 2013Applicant: Fujitsu Semiconductor LimitedInventors: Shinya FUJIOKA, Tomohiro KAWAKUBO, Koichi NISHIMURA, Kotoku SATO
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Publication number: 20130326248Abstract: A semiconductor device includes a memory core with a plurality of memory cells, an internal voltage generator and a low power entry circuit. The low power entry circuit receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited. The internal voltage generator includes a detector and at least one of booster circuits. The internal voltage generator, coupled to the memory core via an internal power supply line, generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line. The internal voltage generator stops supplying the boosted internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device.Type: ApplicationFiled: August 6, 2013Publication date: December 5, 2013Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Shinya Fujioka, Tomohiro Kawakubo, Koichi Nishimura, Kotoku Sato
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Publication number: 20130326247Abstract: A semiconductor device includes a memory core with a plurality of memory cells, an internal voltage generator and a low power entry circuit. The low power entry circuit receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited. The internal voltage generator includes a detector and at least one of booster circuits. The internal voltage generator, coupled to the memory core via an internal power supply line, generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line. The internal voltage generator stops supplying the boosted internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device.Type: ApplicationFiled: August 6, 2013Publication date: December 5, 2013Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Shinya FUJIOKA, Tomohiro Kawakubo, Koichi Nishimura, Kotoku Sato
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Publication number: 20130315020Abstract: A semiconductor device includes a memory core with a plurality of memory cells, an internal voltage generator and a low power entry circuit. The low power entry circuit receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited. The internal voltage generator includes a detector and at least one of booster circuits. The internal voltage generator, coupled to the memory core via an internal power supply line, generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line. The internal voltage generator stops supplying the boosted internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device.Type: ApplicationFiled: August 6, 2013Publication date: November 28, 2013Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Shinya FUJIOKA, Tomohiro Kawakubo, Koichi Nishimura, Kotoku Sato
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Publication number: 20130315012Abstract: A semiconductor device includes a memory core with a plurality of memory cells, an internal voltage generator and a low power entry circuit. The low power entry circuit receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited. The internal voltage generator includes a detector and at least one of booster circuits. The internal voltage generator, coupled to the memory core via an internal power supply line, generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line. The internal voltage generator stops supplying the boosted internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device.Type: ApplicationFiled: August 6, 2013Publication date: November 28, 2013Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Shinya FUJIOKA, Tomohiro KAWAKUBO, Koichi NISHIMURA, Kotoku SATO
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Publication number: 20130318293Abstract: A semiconductor device includes a memory core with a plurality of memory cells, an internal voltage generator and a low power entry circuit. The low power entry circuit receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited. The internal voltage generator includes a detector and at least one of booster circuits. The internal voltage generator, coupled to the memory core via an internal power supply line, generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line. The internal voltage generator stops supplying the boosted internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device.Type: ApplicationFiled: August 6, 2013Publication date: November 28, 2013Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Shinya FUJIOKA, Tomohiro KAWAKUBO, Koichi NISHIMURA, Kotoku SATO
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Publication number: 20120120739Abstract: An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.Type: ApplicationFiled: January 23, 2012Publication date: May 17, 2012Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Shinya FUJIOKA, Tomohiro Kawakubo, Koichi Nishimura, Kotoku Sato
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Patent number: 8130586Abstract: An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.Type: GrantFiled: July 30, 2010Date of Patent: March 6, 2012Assignee: Fujitsu Semiconductor LimitedInventors: Shinya Fujioka, Tomohiro Kawakubo, Koichi Nishimura, Kotoku Sato
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Patent number: 7903487Abstract: An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.Type: GrantFiled: August 29, 2008Date of Patent: March 8, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Shinya Fujioka, Tomohiro Kawakubo, Koichi Nishimura, Kotoku Sato
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Patent number: 7869296Abstract: An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.Type: GrantFiled: September 6, 2006Date of Patent: January 11, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Shinya Fujioka, Tomohiro Kawakubo, Koichi Nishimura, Kotoku Sato
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Publication number: 20100302879Abstract: An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.Type: ApplicationFiled: July 30, 2010Publication date: December 2, 2010Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Shinya FUJIOKA, Tomohiro Kawakubo, Koichi Nishimura, Kotoku Sato
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Patent number: 7730232Abstract: A data transfer method and system are provided that prevent the length of a time required for writing to a flash memory from appearing on the surface as a system operation when the flash memory is used in place of an SRAM. The method of transferring data includes the steps of writing data from a controller to a volatile memory, placing the volatile memory in a transfer state, transferring the data from the volatile memory in the transfer state to a nonvolatile memory, and releasing the volatile memory from the transfer state in response to confirming completion of the transfer of the data.Type: GrantFiled: April 25, 2005Date of Patent: June 1, 2010Assignee: Fujitsu Microelectronics LimitedInventors: Shinya Fujioka, Kotoku Sato, Hitoshi Ikeda, Yoshiaki Okuyama, Jun Ohno
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Patent number: 7688661Abstract: An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.Type: GrantFiled: September 22, 2008Date of Patent: March 30, 2010Assignee: Fujitsu Microelectronics LimitedInventors: Shinya Fujioka, Tomohiro Kawakubo, Koichi Nishimura, Kotoku Sato
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Patent number: 7684258Abstract: To perform mask control of data signals without increasing the number of external terminals even when the number of bits in a data mask signal is large, an address input circuit sequentially receives a first address signal, a second address signal, and a first data mask signal supplied to an address terminal in synchronization with transition edges of a clock signal. Namely, the first data mask signal is supplied to the address terminal at a different timing from timing at which the first and second address signals are received. The first address signal, second address signal, and first data mask signal are output, for example, from a controller accessing a semiconductor memory. A data input/output circuit inputs/outputs data via a data terminal and masks at least either of write data to memory cells and read data from the memory cells in accordance with logic of the first data mask signal.Type: GrantFiled: February 13, 2007Date of Patent: March 23, 2010Assignee: Fujitsu Microelectronics LimitedInventors: Tatsuya Kanda, Kotoku Sato
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Patent number: 7495986Abstract: An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.Type: GrantFiled: July 27, 2005Date of Patent: February 24, 2009Assignee: Fujitsu Microelectronic LimitedInventors: Shinya Fujioka, Tomohiro Kawakubo, Koichi Nishimura, Kotoku Sato
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Patent number: 7483323Abstract: An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.Type: GrantFiled: September 6, 2006Date of Patent: January 27, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Shinya Fujioka, Tomohiro Kawakubo, Koichi Nishimura, Kotoku Sato
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Publication number: 20090016142Abstract: An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.Type: ApplicationFiled: September 22, 2008Publication date: January 15, 2009Inventors: Shinya FUJIOKA, Tomohiro KAWAKUBO, Koichi NISHIMURA, Kotoku SATO