Abstract: A training system for training of part of a trainee's body includes a training machine, a control device controlling the training machine, and a display unit displaying a game screen. The training machine imposes a load on the trainee, with an MR-fluid load generating unit using MR fluid, which has viscosity varying with a magnetic field strength. The load is calculated on the basis of a target load and a relationship between the current in the MR-fluid load generating unit and the load generated by the MR-fluid load generating unit. The control device produces the game screen in correspondence with the trainee's training motion detected by a displacement detection sensor, and makes the display unit display the game screen, while controlling the load in the training machine.

Abstract: A hydraulic pressure control apparatus includes a first pressure regulating valve for reducing an initial oil pressure (line pressure) of a working oil, a solenoid-operated valve for converting the oil pressure, which has been reduced in pressure, into a solenoid pressure, and a second pressure regulating valve for converting the line pressure of the working oil into an actuating pressure responsive to the solenoid pressure. The three valves share a single body. Further, an outlet passageway is formed along a thicknesswise direction of the body, with a relief valve being formed upwardly of the outlet passageway.

Abstract: A hydraulic pressure control apparatus includes a first pressure regulating valve for reducing an initial oil pressure of a working oil introduced from an inlet port, a solenoid-operated valve, and a second pressure regulating valve for converting the initial oil pressure of the working oil into an actuating pressure. The three valves share a single body. A joining boss and a relief valve, which is operable to release the working oil out of a passage in the body when the pressure of the working oil in the passage becomes equal to or greater than a predetermined threshold value, are arranged on a closed end face of the body. The joining boss and the relief valve have respective upper surfaces that are covered by a cover.

Abstract: A first voltage dividing circuit is connected between a power feeding line to feed power from an external power supply to an internal circuit, and a fixed potential to divide a voltage of the power feeding line. A first comparator compares a divided voltage, which has been divided by the first voltage dividing circuit, with a reference voltage, and outputs a signal to turn off a power switch inserted into the power feeding line when the divided voltage exceeds the reference voltage. A first transistor is connected between a first node where the divided voltage, which has been divided by the first voltage dividing circuit, is generated, and the fixed potential, and is turned on when the voltage of the first node exceeds a set voltage.

Abstract: A reversely-rotatable roller conveys a sheet having an image formed on its one side at a sheet conveying velocity faster than that of a conveying roller by normal rotation and then, the reversely-rotatable roller conveys the sheet to a re-conveying path by reverse rotation. The sheet conveying velocity of the reversely-rotatable roller when the reversely-rotatable roller reversely rotates is made slower than the sheet conveying velocity when the reversely-rotatable roller normally rotates so that the sheet conveying velocity of the re-conveying roller is substantially equal to or slower than the sheet conveying velocity of the conveying roller.

Abstract: A MOS transistor includes a gate electrode formed in a grid pattern, source regions and drain regions each surrounded by the gate electrode, and a source metal wiring connected to the source regions via source contacts and a drain metal wiring connected to the drain regions via drain contacts. The source metal wiring and the drain metal wiring are disposed along one direction of the grid of the gate electrode. Each of the source regions and the drain regions is a rectangular form having its long side along the length direction of each metal wiring. The source metal wiring and the drain metal wiring are each formed in a zigzag manner in the length direction and are respectively connected to the source contacts and the drain contacts.

Abstract: In a memory cell including CMOS inverters, an increase in an area of the memory cell caused by restrictions on a gate wiring due to a leakage current and restrictions due to design rules is suppressed. A first wiring and a second wiring are laid out as a first metal layer in the memory cell that includes a first inverter and a second inverter. The first wiring is connected with two drains in the first inverter and a second gate wiring in the second inverter. The second wiring is connected with two drains in the second inverter and a first gate wiring in the first inverter. The first wiring is laid out to overlap with the second gate wiring, and the second wiring is laid out to overlap with the first gate wiring. A second metal layer is laid out above the first metal layer, and a third metal layer is laid out above the second metal layer.

Abstract: An ejector for a fuel cell system of the present invention includes a nozzle having a nozzle hole for discharging hydrogen supplied via an inlet port of an ejector body, a diffuser for mixing hydrogen discharged from the nozzle hole and hydrogen off-gas discharged and returned via a circulation passage from a fuel cell, a needle displacing in the axial direction by a driving force of a solenoid, and a bearing member held in a hollow portion of the nozzle, and having a through hole that movably supports the needle in the axial direction.

Abstract: A first voltage dividing circuit is connected between a power feeding line to feed power from an external power supply to an internal circuit, and a fixed potential to divide a voltage of the power feeding line. A first comparator compares a divided voltage, which has been divided by the first voltage dividing circuit, with a reference voltage, and outputs a signal to turn off a power switch inserted into the power feeding line when the divided voltage exceeds the reference voltage. A first transistor is connected between a first node where the divided voltage, which has been divided by the first voltage dividing circuit, is generated, and the fixed potential, and is turned on when the voltage of the first node exceeds a set voltage.

Abstract: A fourth n-channel MOSFET has a source terminal and a back-gate terminal connected to each other. A switch element is connected between the source terminal of the fourth n-channel MOSFET and a ground potential, and the source terminal of the fourth n-channel MOSFET is made become the ground potential when the fourth n-channel MOSFET is OFF. A protection circuit is provided between a connection node of the source terminal of the fourth n-channel MOSFET and an input terminal of the switch element, and the ground potential so that a negative inflow current from the drain terminal of the fourth n-channel MOSFET caused by electrostatic discharge flows to the ground potential.

Abstract: A training system for training of part of a trainee's body includes a training machine, a control device controlling the training machine, and a display unit displaying a game screen. The training machine imposes a load on the trainee, with an MR-fluid load generating unit using MR fluid, which has viscosity varying with a magnetic field strength. The load is calculated on the basis of a target load and a relationship between the current in the MR-fluid load generating unit and the load generated by the MR-fluid load generating unit. The control device produces the game screen in correspondence with the trainee's training motion detected by a displacement detection sensor, and makes the display unit display the game screen, while controlling the load in the training machine.

Abstract: A floating gate made of polysilicon is provided on a semiconductor substrate through the medium of a gate insulator. A side-wall insulating film is provided on each side wall of the floating gate. A first impurity diffusion layer, which occupies a space within the semiconductor substrate, is provided separately apart from the floating gate by a predetermined distance. A second impurity diffusion layer, which occupies a space within the semiconductor substrate, overlaps with the floating gate. Electrons are injected into the floating gate by applying a high voltage to the second impurity diffusion layer in capacitive coupling with the floating gate.

Abstract: A signal line from a common terminal, which allows the insertion of a terminal of a cable for transmitting high-frequency signals or the insertion of a terminal of a cable dedicated to the transmission of audio signals, is branched into one line which is connected to one end of a high-frequency signal switch (USB switch) and the other line which is connected to one end of an audio signal switch (audio switch), respectively. A signal line from the other end of the high-frequency signal switch is connected to a target circuit. A signal line from the other end of the audio signal switch in a primary hierarchical position is branched into a plurality of lines, and the respective plurality of lines are connected to one end of audio signal switches (e.g., headphone switch and microphone switch) in a secondary hierarchical position. And the respective signal lines from the other end of the plurality of audio signal switches of secondary hierarchical position are connected to respective target circuits.

Abstract: In a bidirectional switch using a metal-oxide-semiconductor field-effect transistor (MOSFET), the source terminal and the backgate terminal of the MOSFET are connected to each other via a transfer gate. A switch may be used between the connection point of the backgate terminal and the transfer gate of the MOSFET and the ground potential (where the MOSFET is an n-channel type) or supply potential (where the MOSFET is a p-channel type).

Abstract: In a memory cell including CMOS inverters, an increase in an area of the memory cell caused by restrictions on a gate wiring due to a leakage current and restrictions due to design rules is suppressed. A first wiring and a second wiring are laid out as a first metal layer in the memory cell that includes a first inverter and a second inverter. The first wiring is connected with two drains in the first inverter and a second gate wiring in the second inverter. The second wiring is connected with two drains in the second inverter and a first gate wiring in the first inverter. The first wiring is laid out to overlap with the second gate wiring, and the second wiring is laid out to overlap with the first gate wiring. A second metal layer is laid out above the first metal layer, and a third metal layer is laid out above the second metal layer.

Abstract: A memory includes conductive layers provided to extend along the word lines, memory cells each including a diode having a cathode connected to the conductive layer and a source line reading data stored in the memory cells, wherein either the conductive layers or the bit lines are in floating states in a standby time.

Abstract: A memory is so formed that, in a first block and a second block each including a prescribed number of the bit lines arranged therein, positions of the bit lines simultaneously selected in the first and second blocks with reference to ends of the first and second blocks respectively are different from each other.

Abstract: In a double edge triggered flip-flop circuit, a first latch circuit latches input data at either one of rising edge and falling edge of clock signal. A second latch circuit, which is provided in parallel with the first latch circuit, latches the input data at the other of the either one of rising edge and falling edge of the clock signal. At least one of the first latch circuit and the second latch circuit is configured by an SRAM (Static Random Access Memory) type.

Abstract: A MOS transistor includes a gate electrode formed in a grid pattern, source regions and drain regions each surrounded by the gate electrode, and a source metal wiring connected to the source regions via source contacts and a drain metal wiring connected to the drain regions via drain contacts. The source metal wiring and the drain metal wiring are disposed along one direction of the grid of the gate electrode. Each of the source regions and the drain regions is a rectangular form having its long side along the length direction of each metal wiring. The source metal wiring and the drain metal wiring are each formed in a zigzag manner in the length direction and are respectively connected to the source contacts and the drain contacts.

Abstract: A power supply circuit generates the internal power supply voltage intVCC from a first power supply capable of supplying a first power supply voltage V1 and a second power supply capable of supplying a second power supply voltage V2, which is lower than the first power supply voltage V1. A first transistor TR1 is provided between the first power supply and an output node, whereas a second transistor TR2 is provided between the second power supply and the output node. A first supply unit supplies the inverted value of an output voltage of the first power supply or the inverted value of a voltage corresponding to the output voltage of the first power supply, to the gate input of the first transistor TR1. A second supply unit supplies the output voltage of the first power supply or the voltage corresponding to the output voltage of the first power supply, to the gate input of the second transistor TR2.