Abstract: A PCM (50) that is an engine control device functions to acquire a master vac negative pressure which is the negative pressure of a stabilized chamber of a master vac (126) which amplifies a brake pedal depressing force applied to a brake pedal (102), and also acquire a brake working fluid pressure that is a braking hydraulic pressure produced by a master cylinder (144) in accordance with the brake pedal depressing force amplified by the master vac (126), and in a case where both accelerator pedal (104) and a brake pedal (102) are depressed or actuated simultaneously, determine whether or not it is necessary to decrease engine output based on such master vac negative pressure and brake working fluid pressure to execute the output decreasing control for decreasing the engine output.

Abstract: A PCM (50) that is an engine control device functions to acquire a master vac negative pressure which is the negative pressure of a stabilized chamber of a master vac (126) which amplifies a brake pedal depressing force applied to a brake pedal (102), and also acquire a brake working fluid pressure that is a braking hydraulic pressure produced by a master cylinder (144) in accordance with the brake pedal depressing force amplified by the master vac (126), and in a case where both accelerator pedal (104) and a brake pedal (102) are depressed or actuated simultaneously, determine whether or not it is necessary to decrease engine output based on such master vac negative pressure and brake working fluid pressure to execute the output decreasing control for decreasing the engine output.

Abstract: A memory TCP loaded with four chips (1-bank 16-bit type) is constructed by a tape of one two-layer wiring layer structure, four chips mounted to this tape, etc. Common signal terminals are arranged on one set of two opposed sides, and an independent signal terminal is arranged on another side. The common signal terminals on the two sides are electrically connected to each other common signal wiring. Further, in a DIMM in which this memory TCP is mounted to front and rear sides of a substrate, plural external terminals are formed on one long side of the rectangular substrate, and the memory TCP is mounted such that the independent signal terminal of the memory TCP is arranged along an arranging direction of these external terminals.

Abstract: A memory TCP loaded with four chips (1-bank 16-bit type) is constructed by a tape of one two-layer wiring layer structure, four chips mounted to this tape, etc. Common signal terminals are arranged on one set of two opposed sides, and an independent signal terminal is arranged on another side. The common signal terminals on the two sides are electrically connected to each other common signal wiring. Further, in a DIMM in which this memory TCP is mounted to front and rear sides of a substrate, plural external terminals are formed on one long side of the rectangular substrate, and the memory TCP is mounted such that the independent signal terminal of the memory TCP is arranged along an arranging direction of these external terminals.

Abstract: A memory TCP loaded with four chips (1-bank 16-bit type) is constructed by a tape of one two-layer wiring layer structure, four chips mounted to this tape, etc. Common signal terminals are arranged on one set of two opposed sides, and an independent signal terminal is arranged on another side. The common signal terminals on the two sides are electrically connected to each other common signal wiring. Further, in a DIMM in which this memory TCP is mounted to front and rear sides of a substrate, plural external terminals are formed on one long side of the rectangular substrate, and the memory TCP is mounted such that the independent signal terminal of the memory TCP is arranged along an arranging direction of these external terminals.