Patents by Inventor Kouji Nakajima

Kouji Nakajima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190097439
    Abstract: A semiconductor device includes a control unit which controls charging/discharging of a secondary battery, a bidirectional coupling unit which is electrically coupled to the control unit and through which a charging/discharging current flows, and a protection diode coupled between the control unit and the bidirectional coupling unit. The bidirectional coupling unit includes a discharging power transistor, a charging power transistor reversely coupled in series with the discharging power transistor, and a common drain pad which functions as a drain of the discharging power transistor and further functions as a drain of the charging power transistor. An anode of the protection diode is electrically coupled to the common drain pad. A cathode of the protection diode is electrically coupled to a power supply terminal of the control unit.
    Type: Application
    Filed: November 28, 2018
    Publication date: March 28, 2019
    Inventors: Keita MOCHIZUKI, Kensuke NAKASHIMA, Takahiro KORENARI, Kouji NAKAJIMA
  • Patent number: 10164447
    Abstract: To provide a semiconductor product high in versatility. A common drain pad is formed over the surface of a semiconductor chip together with source pads and gate pads of discharging and charging power transistors. Thus, when the semiconductor chip is face-down mounted over a wiring board, not only the source pads and gate pads of the discharging and charging power transistors, but also the common drain pad is electrically coupled to wirings of the wiring board.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: December 25, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Keita Mochizuki, Kensuke Nakashima, Takahiro Korenari, Kouji Nakajima
  • Publication number: 20180183427
    Abstract: An object of the present invention is to suppress an increase in on-resistance of an entire circuit including a bidirectional semiconductor switch. A semiconductor device includes a first main MOS transistor and a second main MOS transistor of a vertical structure that are inversely coupled to each other in series by sharing a drain electrode and a first sense MOS transistor and a second sense MOS transistor of a vertical structure that are inversely coupled to each other in series by sharing a drain electrode. The first sense MOS transistor is used for detecting the main current of the first main MOS transistor, and the second sense MOS transistor is used for detecting the main current of the second main MOS transistor.
    Type: Application
    Filed: November 16, 2017
    Publication date: June 28, 2018
    Inventors: Kouji Nakajima, Yoshiaki Tanaka
  • Patent number: 9800889
    Abstract: With use of a simplified program or calculating device for motion compensation, a video decoding device decodes video data compressed by motion detection operations on macroblock units, as in the MPEG-4AVC standard. The video decoding device splits compressed data blocks of the prescribed size, 16×16 pixels for instance, to generate sub-blocks, which are smaller than the blocks and on which the video decoding device is able to execute motion compensation operations. The video decoding device duplicates a motion vector assigned to a given block to generate an many motion vectors as there are sub-blocks in the given block, and executes motion compensation on each sub-block using the corresponding duplicate motion vector. Data resulting from the motion compensation operation on each sub-block is combined to obtain a target block corresponding to the given block.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: October 24, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Hiroshi Amano, Takeshi Tanaka, Kouji Nakajima, Eiji Otomura
  • Patent number: 9697004
    Abstract: A Very Long Instruction Word (VLIW) processor having an instruction set with a reduced size resulting in a small number of bits being necessary to specify registers. The VLIW processor includes a register file, and first through third operation units, and executes a very long instruction word. Further, the very long instruction word includes a register specifying field which specifies a least one of the registers in the register file and a plurality of instructions. The operand of each instruction includes bits src1, src2, and dst, which indicate whether or not the registers specified by the register specifying field are to be used as the source register and the destination register.
    Type: Grant
    Filed: April 8, 2014
    Date of Patent: July 4, 2017
    Assignee: SOCIONEXT INC.
    Inventors: Takahiro Kageyama, Hideshi Nishida, Takeshi Tanaka, Kouji Nakajima
  • Publication number: 20170048541
    Abstract: With use of a simplified program or calculating device for motion compensation, a video decoding device decodes video data compressed by motion detection operations on macroblock units, as in the MPEG-4AVC standard. The video decoding device splits compressed data blocks of the prescribed size, 16×16 pixels for instance, to generate sub-blocks, which are smaller than the blocks and on which the video decoding device is able to execute motion compensation operations. The video decoding device duplicates a motion vector assigned to a given block to generate an many motion vectors as there are sub-blocks in the given block, and executes motion compensation on each sub-block using the corresponding duplicate motion vector. Data resulting from the motion compensation operation on each sub-block is combined to obtain a target block corresponding to the given block.
    Type: Application
    Filed: October 31, 2016
    Publication date: February 16, 2017
    Inventors: Hiroshi Amano, Takeshi Tanaka, Kouji Nakajima, Eiji Otomura
  • Patent number: 9516336
    Abstract: With use of a simplified program or calculating device for motion compensation, a video decoding device decodes video data compressed by motion detection operations on macroblock units, as in the MPEG-4AVC standard. The video decoding device splits compressed data blocks of the prescribed size, 16×16 pixels for instance, to generate sub-blocks, which are smaller than the blocks and on which the video decoding device is able to execute motion compensation operations. The video decoding device duplicates a motion vector assigned to a given block to generate as many motion vectors as there are sub-blocks in the given block, and executes motion compensation on each sub-block using the corresponding duplicate motion vector. Data resulting from the motion compensation operation on each sub-block is combined to obtain a target block corresponding to the given block.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: December 6, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Hiroshi Amano, Takeshi Tanaka, Kouji Nakajima, Eiji Otomura
  • Publication number: 20160254809
    Abstract: To provide a semiconductor product high in versatility. A common drain pad is formed over the surface of a semiconductor chip together with source pads and gate pads of discharging and charging power transistors. Thus, when the semiconductor chip is face-down mounted over a wiring board, not only the source pads and gate pads of the discharging and charging power transistors, but also the common drain pad is electrically coupled to wirings of the wiring board.
    Type: Application
    Filed: November 19, 2015
    Publication date: September 1, 2016
    Inventors: Keita MOCHIZUKI, Kensuke NAKASHIMA, Takahiro KORENARI, Kouji NAKAJIMA
  • Patent number: 9063794
    Abstract: A computer system includes: a main storage unit, a processing executing unit sequentially executing processing to be executed on virtual processors; a level-1 cache memory shared among the virtual processors; a level-2 cache memory including storage areas partitioned based on the number of the virtual processors, the storage areas each (i) corresponding to one of the virtual processors and (ii) holding the data to be used by the corresponding one of the virtual processors; a context memory holding a context item corresponding to the virtual processor; a virtual processor control unit saving and restoring a context item of one of the virtual processors; a level-1 cache control unit; and a level-2 cache control unit.
    Type: Grant
    Filed: October 4, 2012
    Date of Patent: June 23, 2015
    Assignee: SOCIONEXT INC.
    Inventors: Teruyuki Morita, Yoshihiro Koga, Kouji Nakajima
  • Publication number: 20140369412
    Abstract: With use of a simplified program or calculating device for motion compensation, a video decoding device decodes video data compressed by motion detection operations on macroblock units, as in the MPEG-4AVC standard. The video decoding device splits compressed data blocks of the prescribed size, 16×16 pixels for instance, to generate sub-blocks, which are smaller than the blocks and on which the video decoding device is able to execute motion compensation operations. The video decoding device duplicates a motion vector assigned to a given block to generate as many motion vectors as there are sub-blocks in the given block, and executes motion compensation on each sub-block using the corresponding duplicate motion vector. Data resulting from the motion compensation operation on each sub-block is combined to obtain a target block corresponding to the given block.
    Type: Application
    Filed: August 28, 2014
    Publication date: December 18, 2014
    Inventors: Hiroshi Amano, Takeshi Tanaka, Kouji Nakajima, Eiji Otomura
  • Patent number: 8873631
    Abstract: With use of a simplified program or calculating device for motion compensation, a video decoding device decodes video data compressed by motion detection operations on macroblock units, as in the MPEG-4AVC standard. The video decoding device splits compressed data blocks of the prescribed size, 16×16 pixels for instance, to generate sub-blocks, which are smaller than the blocks and on which the video decoding device is able to execute motion compensation operations. The video decoding device duplicates a motion vector assigned to a given block to generate as many motion vectors as there are sub-blocks in the given block, and executes motion compensation on each sub-block using the corresponding duplicate motion vector. Data resulting from the motion compensation operation on each sub-block is combined to obtain a target block corresponding to the given block.
    Type: Grant
    Filed: May 7, 2013
    Date of Patent: October 28, 2014
    Assignee: Panasonic Corporation
    Inventors: Hiroshi Amano, Takeshi Tanaka, Kouji Nakajima, Eiji Otomura
  • Publication number: 20140223142
    Abstract: A Very Long Instruction Word (VLIW) processor having an instruction set with a reduced size resulting in a small number of bits being necessary to specify registers. The VLIW processor includes a register file, and first through third operation units, and executes a very long instruction word. Further, the very long instruction word includes a register specifying field which specifies a least one of the registers in the register file and a plurality of instructions. The operand of each instruction includes bits src1, src2, and dst, which indicate whether or not the registers specified by the register specifying field are to be used as the source register and the destination register.
    Type: Application
    Filed: April 8, 2014
    Publication date: August 7, 2014
    Applicant: Panasonic Corporation
    Inventors: Takahiro KAGEYAMA, Hideshi NISHIDA, Takeshi TANAKA, Kouji NAKAJIMA
  • Patent number: 8738892
    Abstract: A Very Long Instruction Word (VLIW) processor having an instruction set with a reduced size resulting in a small number of bits being necessary to specify registers. The VLIW processor includes a register file, and first through third operation units, and executes a very long instruction word. Further, the very long instruction word includes a register specifying field which specifies a least one of the registers in the register file and a plurality of instructions. The operand of each instruction includes bits src1, src2, and dst, which indicate whether or not the registers specified by the register specifying field are to be used as the source register and the destination register.
    Type: Grant
    Filed: April 15, 2008
    Date of Patent: May 27, 2014
    Assignee: Panasonic Corporation
    Inventors: Takahiro Kageyama, Hideshi Nishida, Takeshi Tanaka, Kouji Nakajima
  • Patent number: 8654847
    Abstract: With use of a simplified program or calculating device for motion compensation, a video decoding device decodes video data compressed by motion detection operations on macroblock units, as in the MPEG-4AVC standard. The video decoding device splits compressed data blocks of the prescribed size, 16×16 pixels for instance, to generate sub-blocks, which are smaller than the blocks and on which the video decoding device is able to execute motion compensation operations. The video decoding device duplicates a motion vector assigned to a given block to generate as many motion vectors as there are sub-blocks in the given block, and executes motion compensation on each sub-block using the corresponding duplicate motion vector. Data resulting from the motion compensation operation on each sub-block is combined to obtain a target block corresponding to the given block.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: February 18, 2014
    Assignee: Panasonic Corporation
    Inventors: Hiroshi Amano, Takeshi Tanaka, Kouji Nakajima, Eiji Otomura
  • Publication number: 20130318544
    Abstract: A program generation device for generating, from a source program, machine programs corresponding to a plurality of processors having different instruction sets and sharing a memory, the program generation device including: a switch point determination unit for determining a switch point in the source program; a switchable-program generation unit for generating a switchable program for each processor so that a data structure of the memory is commonly shared at a switch point among the plurality of processors; and a switch decision process insertion unit for inserting into the switchable programs a switch program for stopping at the switch point a switchable program being executed by and corresponding to a first processor, and causing a second processor to execute, from the switch point, a switchable program corresponding to the second processor.
    Type: Application
    Filed: July 29, 2013
    Publication date: November 28, 2013
    Applicant: PANASONIC CORPORATION
    Inventors: Manabu KURODA, Yoshihiro KOGA, Kunihiko HAYASHI, Kouji NAKAJIMA
  • Patent number: 8588304
    Abstract: With use of a simplified program or calculating device for motion compensation, a video decoding device decodes video data compressed by motion detection operations on macroblock units, as in the MPEG-4AVC standard. The video decoding device splits compressed data blocks of the prescribed size, 16×16 pixels for instance, to generate sub-blocks, which are smaller than the blocks and on which the video decoding device is able to execute motion compensation operations. The video decoding device duplicates a motion vector assigned to a given block to generate as many motion vectors as there are sub-blocks in the given block, and executes motion compensation on each sub-block using the corresponding duplicate motion vector. Data resulting from the motion compensation operation on each sub-block is combined to obtain a target block corresponding to the given block.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: November 19, 2013
    Assignee: Panasonic Corporation
    Inventors: Hiroshi Amano, Takeshi Tanaka, Kouji Nakajima, Eiji Otomura
  • Publication number: 20130243096
    Abstract: With use of a simplified program or calculating device for motion compensation, a video decoding device decodes video data compressed by motion detection operations on macroblock units, as in the MPEG-4AVC standard. The video decoding device splits compressed data blocks of the prescribed size, 16×16 pixels for instance, to generate sub-blocks, which are smaller than the blocks and on which the video decoding device is able to execute motion compensation operations. The video decoding device duplicates a motion vector assigned to a given block to generate as many motion vectors as there are sub-blocks in the given block, and executes motion compensation on each sub-block using the corresponding duplicate motion vector. Data resulting from the motion compensation operation on each sub-block is combined to obtain a target block corresponding to the given block.
    Type: Application
    Filed: May 7, 2013
    Publication date: September 19, 2013
    Applicant: Panasonic Corporation
    Inventors: Hiroshi Amano, Takeshi Tanaka, Kouji Nakajima, Eiji Otomura
  • Publication number: 20120202342
    Abstract: A method of manufacturing a semiconductor device includes depositing a wiring metal layer on a photoresist layer and a portion of a first layer of a gate lead-out electrode which is exposed via an opening, lifting-off a wiring metal layer formed on the photoresist layer forming an interlayer insulation film over the entire surface including the first layer and the wiring metal layer, selectively removing the interlayer insulation film thereby forming a contact via reaching a source region formed in a cell region, and forming a source electrode on the interlayer insulation film and electrically connecting a source electrode with the source region.
    Type: Application
    Filed: April 18, 2012
    Publication date: August 9, 2012
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Kouji NAKAJIMA
  • Patent number: 8183645
    Abstract: Flexibility for the design of the pattern layout of the gate lead-out electrode and the source electrode is enhanced without increasing the chip thickness of the semiconductor device. A semiconductor device includes a cell region where plural transistor cells are arranged and a gate finger region different from a region where the cell region is formed. In the cell region, a gate electrode formed of a polysilicon (first conductive material) is formed. A polysilicon layer formed indivisibly with the gate electrode is formed in the gate finger region. An adhesion metal layer and a wiring metal layer are formed above the polysilicon layer by a lift-off method. The gate lead-out electrode is formed of a laminate structure including the polysilicon layer, the adhesion metal layer, and the wiring metal layer. A single layer of interlayer insulation film covering them is formed, on which a source electrode is formed.
    Type: Grant
    Filed: October 14, 2009
    Date of Patent: May 22, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Kouji Nakajima
  • Publication number: 20120087413
    Abstract: With use of a simplified program or calculating device for motion compensation, a video decoding device decodes video data compressed by motion detection operations on macroblock units, as in the MPEG-4AVC standard. The video decoding device splits compressed data blocks of the prescribed size, 16×16 pixels for instance, to generate sub-blocks, which are smaller than the blocks and on which the video decoding device is able to execute motion compensation operations. The video decoding device duplicates a motion vector assigned to a given block to generate as many motion vectors as there are sub-blocks in the given block, and executes motion compensation on each sub-block using the corresponding duplicate motion vector. Data resulting from the motion compensation operation on each sub-block is combined to obtain a target block corresponding to the given block.
    Type: Application
    Filed: December 16, 2011
    Publication date: April 12, 2012
    Applicant: Panasonic Corporation
    Inventors: Hiroshi Amano, Takeshi Tanaka, Kouji Nakajima, Eiji Otomura