Patents by Inventor Kozo Makiyama

Kozo Makiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9324821
    Abstract: An embodiment of a compound semiconductor device includes: a substrate; a nitride compound semiconductor stacked structure formed on or above the substrate; and a gate electrode, a source electrode and a drain electrode formed on or above the compound semiconductor stacked structure. A recess positioning between the gate electrode and the drain electrode in a plan view is formed at a surface of the compound semiconductor stacked structure.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: April 26, 2016
    Assignee: FUJITSU LIMITED
    Inventor: Kozo Makiyama
  • Publication number: 20160099335
    Abstract: A semiconductor device includes: a first electrode; a second electrode; an interlayer insulating film made of a porous insulating material and formed above the first electrode and the second electrode; and connection parts electrically connected to the first electrode and the second electrode respectively, wherein a cavity is formed between the interlayer insulating film and a surface of the first electrode, a surface of the second electrode, and parts of surfaces of the connection parts.
    Type: Application
    Filed: December 11, 2015
    Publication date: April 7, 2016
    Applicant: FUJITSU LIMITED
    Inventors: Shirou OZAKI, Naoya OKAMOTO, Kozo MAKIYAMA, Toshihiro OHKI
  • Publication number: 20160049290
    Abstract: A semiconductor device includes: a compound semiconductor stack structure including a plurality of compound semiconductor layers stacked over a semiconductor substrate; and a first insulating film covering the surface of the compound semiconductor stack structure, the first insulating film being a silicon nitride film including, on the top side, a first region containing nitrogen element in excess of the stoichiometric ratio.
    Type: Application
    Filed: October 29, 2015
    Publication date: February 18, 2016
    Applicant: FUJITSU LIMITED
    Inventor: Kozo Makiyama
  • Patent number: 9257514
    Abstract: A semiconductor device includes: a first electrode; a second electrode; an interlayer insulating film made of a porous insulating material and formed above the first electrode and the second electrode; and connection parts electrically connected to the first electrode and the second electrode respectively, wherein a cavity is formed between the interlayer insulating film and a surface of the first electrode, a surface of the second electrode, and parts of surfaces of the connection parts.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: February 9, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Shirou Ozaki, Naoya Okamoto, Kozo Makiyama, Toshihiro Ohki
  • Patent number: 9224668
    Abstract: A semiconductor device includes: a compound semiconductor stack structure including a plurality of compound semiconductor layers stacked over a semiconductor substrate; and a first insulating film covering the surface of the compound semiconductor stack structure, the first insulating film being a silicon nitride film including, on the top side, a first region containing nitrogen element in excess of the stoichiometric ratio.
    Type: Grant
    Filed: December 3, 2013
    Date of Patent: December 29, 2015
    Assignee: FUJITSU LIMITED
    Inventor: Kozo Makiyama
  • Patent number: 9209042
    Abstract: A compound semiconductor device includes a compound semiconductor laminated structure, a passivation film formed on the compound semiconductor laminated structure and having a through-hole, and a gate electrode formed on the passivation film so as to plug the through-hole. A grain boundary between different crystalline orientations is formed in the gate electrode, and a starting point of the grain boundary is located apart from the through-hole on a flat surface of the passivation film.
    Type: Grant
    Filed: June 11, 2014
    Date of Patent: December 8, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Naoya Okamoto, Kozo Makiyama, Toshihiro Ohki, Yuichi Minoura, Shirou Ozaki, Toyoo Miyajima
  • Publication number: 20150333135
    Abstract: A compound semiconductor device includes: a compound semiconductor layer; a protective insulating film that covers a top of the compound semiconductor layer; and a gate electrode formed on the protective insulating film, wherein the protective insulating film has a first trench and a second trench which is formed side by side with the first trench and in which the protective insulating film remains with only a predetermined thickness on the compound semiconductor layer, and wherein the gate electrode fills the first trench, and one end of the gate electrode is away from the first trench and located at least in the second trench.
    Type: Application
    Filed: July 29, 2015
    Publication date: November 19, 2015
    Inventors: Kozo MAKIYAMA, Naoya Okamoto, Toshihide Kikkawa
  • Patent number: 9184272
    Abstract: A compound semiconductor device includes: a compound semiconductor layer; a protective insulating film that covers a top of the compound semiconductor layer; and a gate electrode formed on the protective insulating film, wherein the protective insulating film has a first trench and a second trench which is formed side by side with the first trench and in which the protective insulating film remains with only a predetermined thickness on the compound semiconductor layer, and wherein the gate electrode fills the first trench, and one end of the gate electrode is away from the first trench and located at least in the second trench.
    Type: Grant
    Filed: July 1, 2013
    Date of Patent: November 10, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Kozo Makiyama, Naoya Okamoto, Toshihide Kikkawa
  • Patent number: 9184273
    Abstract: An embodiment of a compound semiconductor device includes: a substrate; a compound semiconductor stacked structure of nitride over the substrate; a passivation film that covers the compound semiconductor stacked structure; a gate electrode, a source electrode, and a drain electrode at a level above the compound semiconductor stacked structure; and an Si—C bond containing film that contains an Si—C bond and includes a part between the source electrode and the drain electrode. The part contacts at least a part of an upper surface of the compound semiconductor stacked structure or at least a part of an upper surface of the passivation film.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: November 10, 2015
    Assignee: FUJITSU LIMITED
    Inventor: Kozo Makiyama
  • Publication number: 20150303291
    Abstract: A semiconductor device includes a first semiconductor layer made of a nitride semiconductor and formed on a substrate, a second semiconductor layer made of a material including InAlN and formed on the first semiconductor layer, an insulator layer formed by an oxidized surface part of the second semiconductor layer, a gate electrode formed on the insulator layer, and a source electrode and a drain electrode respectively formed on the first or second semiconductor layer.
    Type: Application
    Filed: April 16, 2015
    Publication date: October 22, 2015
    Inventors: Kozo Makiyama, Shirou OZAKI
  • Patent number: 9035353
    Abstract: A HEMT has a compound semiconductor layer, a protection film which has an opening and covers an upper side of the compound semiconductor layer, and a gate electrode which fills the opening and has a shape riding on the compound semiconductor layer, wherein the protection film has a stacked structure of a lower insulating film not containing oxygen and an upper insulating film containing oxygen, and the opening includes a first opening formed in the lower insulating film and a second opening formed in the upper insulating film and wider than the first opening, the first opening and the second opening communicating with each other.
    Type: Grant
    Filed: August 6, 2012
    Date of Patent: May 19, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Toshihiro Ohki, Naoya Okamoto, Yuichi Minoura, Kozo Makiyama, Shirou Ozaki
  • Patent number: 9035357
    Abstract: An HEMT includes, on an SiC substrate, a compound semiconductor layer, a silicon nitride (SiN) protective film having an opening and covering the compound semiconductor layer, and a gate electrode formed on the compound semiconductor layer so as to plug the opening. In the protective film, a projecting portion projecting from a side surface of the opening is formed at a lower layer portion 6a.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: May 19, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Kozo Makiyama, Naoya Okamoto, Toshihiro Ohki, Yuichi Minoura, Shirou Ozaki, Toyoo Miyajima
  • Patent number: 8999772
    Abstract: Two layers of protection films are formed such that a sheet resistance at a portion directly below the protection film is higher than that at a portion directly below the protection film. The protection films are formed, for example, of SiN film, as insulating films. The protection film is formed to be higher, for instance, in hydrogen concentration than the protection film so that the protection film is higher in refractive index the protection film. The protection film is formed to cover a gate electrode and extend to the vicinity of the gate electrode on an electron supplying layer. The protection film is formed on the entire surface to cover the protection film. According to this configuration, the gate leakage is significantly reduced by a relatively simple configuration to realize a highly-reliable compound semiconductor device achieving high voltage operation, high withstand voltage, and high output.
    Type: Grant
    Filed: October 23, 2014
    Date of Patent: April 7, 2015
    Assignee: Fujitsu Limited
    Inventors: Masahito Kanamura, Kozo Makiyama
  • Patent number: 8980768
    Abstract: A protective insulation film covering a surface of a compound semiconductor region is formed to have a two-layer structure of a first insulation film and a second insulation film which have different properties. The first insulation film is a non-stoichiometric silicon nitride film while the second insulation film is a silicon nitride film in an almost stoichiometric state.
    Type: Grant
    Filed: October 16, 2013
    Date of Patent: March 17, 2015
    Assignee: Fujitsu Limited
    Inventor: Kozo Makiyama
  • Publication number: 20150060946
    Abstract: A compound semiconductor device includes a channel layer of first arsenide semiconductor, an electron supply layer of second arsenide semiconductor over the channel layer, a gate electrode, a source electrode and a drain electrode over the channel layer, and a metal film between the gate electrode and the drain electrode, the metal film being insulated from the gate electrode and the drain electrode.
    Type: Application
    Filed: July 22, 2014
    Publication date: March 5, 2015
    Inventor: Kozo Makiyama
  • Publication number: 20150044825
    Abstract: Two layers of protection films are formed such that a sheet resistance at a portion directly below the protection film is higher than that at a portion directly below the protection film. The protection films are formed, for example, of SiN film, as insulating films. The protection film is formed to be higher, for instance, in hydrogen concentration than the protection film so that the protection film is higher in refractive index the protection film. The protection film is formed to cover a gate electrode and extend to the vicinity of the gate electrode on an electron supplying layer. The protection film is formed on the entire surface to cover the protection film. According to this configuration, the gate leakage is significantly reduced by a relatively simple configuration to realize a highly-reliable compound semiconductor device achieving high voltage operation, high withstand voltage, and high output.
    Type: Application
    Filed: October 23, 2014
    Publication date: February 12, 2015
    Inventors: Masahito Kanamura, Kozo Makiyama
  • Patent number: 8916459
    Abstract: A compound semiconductor device having mesa-shaped element region, and excellent characteristics are provided. The compound semiconductor device has: an InP substrate; an epitaxial lamination mesa formed above the InP substrate and including a channel layer, a carrier supply layer above the channel layer and a contact cap layer above the carrier supply layer; ohmic source electrode and drain electrode formed on the cap layer; a recess formed by removing the cap layer between the source and drain electrodes, and exposing the carrier supply layer; an insulating film formed on the cap layer and retracted from an edge of the cap layer away from the recess; a gate electrode extending from the carrier supply layer in the recess to outside of the mesa; and air gap formed by removing side portion of the channel layer facing the gate electrode outside the mesa.
    Type: Grant
    Filed: October 30, 2013
    Date of Patent: December 23, 2014
    Assignee: Fujitsu Limited
    Inventors: Tsuyoshi Takahashi, Kozo Makiyama
  • Publication number: 20140367694
    Abstract: A semiconductor device includes a first semiconductor layer configured to be formed of a nitride semiconductor on a substrate; a second semiconductor layer configured to be formed of a nitride semiconductor on the first semiconductor layer; an insulation film configured to include an opening, and to be formed on the second semiconductor layer; a source electrode and a drain electrode configured to be formed on the second semiconductor layer; and a gate electrode configured to be formed at the opening on the second semiconductor layer. Both the insulation film and the second semiconductor layer include carbon in a neighborhood of an interface between the insulation film and the second semiconductor layer.
    Type: Application
    Filed: June 11, 2014
    Publication date: December 18, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Youichi KAMADA, Shirou OZAKI, Toshihiro Ohki, Kozo Makiyama, NAOYA OKAMOTO
  • Patent number: 8907379
    Abstract: A semiconductor device has a semiconductor region including a gate electrode disposed over the semiconductor region, a first electrode portion, a second electrode portion standing substantially perpendicular to a surface of the semiconductor region and a substantially constant dimension in a direction parallel to the surface of the semiconductor region. The semiconductor device has a tapered portion disposed between the first electrode portion and the second electrode portion and has a dimension parallel to the surface of the semiconductor region increasing in the direction from the second electrode portion to the first electrode portion. Further, the semiconductor device includes a source and a drain electrode at both sides of the gate electrode over the semiconductor region and an insulating layer that covers a portion of the surface of the semiconductor region. Additionally, the second electrode portion may be positioned closer to one of the drain electrode and the source electrode.
    Type: Grant
    Filed: September 15, 2013
    Date of Patent: December 9, 2014
    Assignee: Fujitsu Limited
    Inventors: Naoko Kurahashi, Kozo Makiyama
  • Patent number: 8895378
    Abstract: Two layers of protection films are formed such that a sheet resistance at a portion directly below the protection film is higher than that at a portion directly below the protection film. The protection films are formed, for example, of SiN film, as insulating films. The protection film is formed to be higher, for instance, in hydrogen concentration than the protection film so that the protection film is higher in refractive index the protection film. The protection film is formed to cover a gate electrode and extend to the vicinity of the gate electrode on an electron supplying layer. The protection film is formed on the entire surface to cover the protection film. According to this configuration, the gate leakage is significantly reduced by a relatively simple configuration to realize a highly-reliable compound semiconductor device achieving high voltage operation, high withstand voltage, and high output.
    Type: Grant
    Filed: October 10, 2013
    Date of Patent: November 25, 2014
    Assignee: Fujitsu Limited
    Inventors: Masahito Kanamura, Kozo Makiyama