Abstract: A method of forming a high thermal conductivity diamond film and its associated structures comprising selectively nucleating a region of a substrate, and forming a diamond film on the substrate such that the diamond film has large grains, which are at least about 20 microns in size. Thus, the larger grained diamond film has greatly improved thermal management capabilities and improves the efficiency and speed of a microelectronic device.

Abstract: A method of coupling a single crystal semiconductor layer to a support substrate. Thinning the single crystal layer. Introducing an integrated circuit into the single crystal layer. And removing the thinned single crystal layer with the integrated circuit from the support substrate.

Abstract: An apparatus includes a carbon nanotube coupled with a first device and a second device of an integrated circuit, wherein electrons can flow between the first device and the second device along the carbon nanotube. Doped amorphous carbon is deposited on the integrated circuit structure. The doped amorphous carbon is planarizing and patterned to form a trench. Carbon based precursor material is deposited in the trench. The carbon based precursor material is converted into the carbon nanotube, wherein the carbon nanotube connects the first device with the second device.

Abstract: A switch structure having multiple contact surfaces that may contact each other. One or more of the contact surfaces may be coated with a resilient material such as diamond.

Abstract: A switch structure having multiple contact surfaces that may contact each other. One or more of the contact surfaces may be coated with a resilient material such as diamond.

Abstract: An apparatus includes a carbon nanotube coupled with a first device and a second device of an integrated circuit, wherein electrons can flow between the first device and the second device along the carbon nanotube. Doped amorphous carbon is deposited on the integrated circuit structure. The doped amorphous carbon is planarizing and patterned to form a trench. Carbon based precursor material is deposited in the trench. The carbon based precursor material is converted into the carbon nanotube, wherein the carbon nanotube connects the first device with the second device.

Abstract: Techniques include heating a substantially uniformly boron-doped wafer to achieve a significantly increased resistivity in a near-surface region of the wafer and forming at least one electrical circuit element in the near-surface region. Integrated circuits or other devices may include a semiconductor wafer with a substantially uniformly boron-doped bulk region and a reduced boron concentration layer near a surface of the wafer. An electrical circuit element may be provided in the reduced boron concentration layer.

Abstract: A double gate silicon over insulator transistor may be formed wherein the bottom gate electrode is formed of a doped diamond film. The doped diamond film may be formed in the process of semiconductor manufacture resulting in an embedded electrode. The diamond film may be advantageous as a heat spreader.

Abstract: A switch structure having multiple contact surfaces that may contact each other. One or more of the contact surfaces may be coated with a resilient material such as diamond.

Abstract: An apparatus includes a carbon nanotube coupled with a first device and a second device of an integrated circuit, wherein electrons can flow between the first device and the second device along the carbon nanotube. Doped amorphous carbon is deposited on the integrated circuit structure. The doped amorphous carbon is planarizing and patterned to form a trench. Carbon based precursor material is deposited in the trench. The carbon based precursor material is converted into the carbon nanotube, wherein the carbon nanotube connects the first device with the second device.

Abstract: Processes are described whereby a wafer is manufactured, a die from the wafer, and an electronic assembly including the die. The die has a diamond layer which primarily serves to spread heat from hot spots of an integrated circuit in the die.

Abstract: Manufacturing a semiconductor wafer includes growing a silicon ingot substantially uniformly doped with boron. The ingot has a resistivity in a range of about 10 to 400 milli-ohm-centimeter and is sliced into individual wafers. The wafers are heated in an atmosphere containing hydrogen at a temperature of at least about 1,000° C. so that a significant amount of boron diffuses out of a near-surface region of the wafers. For example, after heating the wafers, the resistivity of the near-surface region of the wafers can be in the range of about 0.5 to 10 ohm-centimeter. Wafers made using the foregoing technique are particularly suited for the fabrication of CMOS integrated circuits. Even in the absence of an epitaxial layer, the lighter doping of the near-surface reduced boron concentration region enables circuit fabrication while the heavier doping of the bulk region of the wafer can help prevent the occurrence of latch-up. The technique can significantly reduce the cost of CMOS fabrication.

Abstract: An apparatus having a single crystal semiconductor layer on a surface of a substrate comprising a polycrystalline semiconductor material such that the single crystal layer and the polycrystalline material are in direct contact.

Abstract: Techniques include heating a substantially uniformly boron-doped wafer to achieve a significantly increased resistivity in a near-surface region of the water and forming at least one electrical circuit element in the near-surface region.

Abstract: A method of coupling a single crystal semiconductor layer on a surface of a substrate comprising a polycrystalline semiconductor material such that the single crystal layer and the polycrystalline material are in direct contact.

Abstract: A substrate for reflective EUV lithography that includes a first layer that has a low coefficient of thermal expansion and a second layer, formed on the first layer, that has a high surface quality. The second layer may have a coefficient of thermal expansion that is higher than the coefficient of thermal expansion of the first layer.

Abstract: A method of coupling a single crystal semiconductor layer to a support substrate. Thinning the single crystal layer. Introducing an integrated circuit into the single crystal layer. And removing the thinned single crystal layer with the integrated circuit from the support substrate.

Abstract: A method of making a wafer is provided. A first semiconductor film is formed onto a semiconductor substrate. An epitaxial film is formed onto an epitaxial wafer. The epitaxial wafer is placed with the epitaxial film on the first semiconductor film. The epitaxial film is debonded from the EPI wafer. The epitaxial film is bonded to the first semiconductor film.

Abstract: A dual wafer processing apparatus (4) includes a chamber housing (14) defining an interior and having upper, lower and central portions (18, 20, 16). An electrostatic chuck (34) has electrostatic chucking surfaces (38, 40) on opposite sides. The chuck is rotatably mounted within the chamber housing so that the chucking surfaces face the upper and lower portions of the chamber housing. After a wafer (36) is positioned on a chucking surface, electrostatic forces are used to maintain the wafer secured to the chucking surface. The chuck is then rotated 180.degree. to permit placement of a second wafer on the second chucking surface. Processing of the two wafers occurs simultaneously. Electrostatic chucking surfaces could be replaced by mechanical wafer clamps.

Abstract: A method and apparatus for depositing a halogen-doped oxide film having a low dielectric constant that is resistant to moisture absorption and outgassing of the halogen dopant, and that retains these qualities despite subsequent processing steps. The method begins by introducing process gases (including a halogen-containing source gas) into a processing chamber. A halogen-doped layer is then deposited. The combination of process gases is then changed and a sealing layer deposited which seals the dopant into the halogen-doped layer. The sealing layer may, for example, be a carbon-rich layer or an undoped layer. These steps are repeated until the film reaches a selected thickness.