Patents by Inventor Krishna Garlapati

Krishna Garlapati has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230096887
    Abstract: Apparatuses, systems, and techniques to operate a network switching device using predicated instructions that implement conditional algorithms of data packet processing are disclosed. The disclosed techniques relate to compiling source codes into objects codes for execution on target network switching devices as well as the actual execution of such compiled object codes. Compilation of a source code may include identifying conditional instructions (CIs) in the source code, which specify contingent actions to be performed by the NSD on a data packet, and compiling the identified CIs to generate corresponding sets of predicated instructions (PIs) of the object code executable by the NSD.
    Type: Application
    Filed: November 18, 2021
    Publication date: March 30, 2023
    Inventors: Stephen Warren, Krishna Garlapati
  • Publication number: 20220261523
    Abstract: Disclosed methods and systems involve, prior to mapping logic of the module to a target integrated circuit (IC) technology, estimating total delay of a module of a circuit design and determining whether or not the module is timing critical based on the total delay of the module and a timing constraint. Also prior to mapping, the module is restructured for timing optimization in response to determining that the module is timing critical. In response to determining that the module is not timing critical, and prior to mapping, the module is restructured for area optimization. The elements of the module are then mapped to the circuit elements of the target IC technology, followed by place-and-route and generating implementation data for making an IC that implements the circuit design.
    Type: Application
    Filed: February 17, 2021
    Publication date: August 18, 2022
    Applicant: Xilinx, Inc.
    Inventors: FAN ZHANG, CHAITHANYA DUDHA, NITHIN KUMAR GUGGILLA, KRISHNA GARLAPATI
  • Patent number: 11188697
    Abstract: Determining on-chip memory access patterns can include modifying a circuit design to include a profiler circuit for a random-access memory (RAM) of the circuit design, wherein the profiler circuit is configured to monitor an address bus of the RAM, and modifying the circuit design to include a debug circuit connected to the profiler circuit. Usage data for the RAM can be generated by detecting, using the profiler circuit, addresses of the RAM accessed during a test of the circuit design, as implemented in an integrated circuit. The usage data for the RAM can be output using the debug circuit.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: November 30, 2021
    Assignee: Xilinx, Inc.
    Inventors: Chaithanya Dudha, Rajeev Patwari, Nithin Kumar Guggilla, Ashish Sirasao, Krishna Garlapati
  • Patent number: 10990736
    Abstract: Implementing a circuit design can include detecting, using computer hardware, a re-convergent section of a circuit design, masking, using the computer hardware, a sequential circuit element of the re-convergent section located between a start and an end of the re-convergent section, and performing, using the computer hardware, an optimization operation on combinatorial logic of the re-convergent section to create optimized combinatorial logic. Using the computer hardware, the optimized combinatorial logic of the re-convergent section can be mapped. Further, the re-convergent section can be modified subsequent to the mapping to match timing of the re-convergent section prior to the masking.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: April 27, 2021
    Assignee: Xilinx, Inc.
    Inventors: Chaithanya Dudha, Satyaprakash Pareek, Krishna Garlapati, Ashish Sirasao
  • Patent number: 10430539
    Abstract: Methods and apparatus relating generally to synthesis are described. In such a method, a directed graph for a circuit design is generated. A cascaded chain is identified in the directed graph with a timing violation. A pipeline register stage of the cascaded chain is moved (or added) to remove the timing violation. The circuit design is transformed to provide a netlist including the pipeline register stage.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: October 1, 2019
    Assignee: XILINX, INC.
    Inventors: Chaithanya Dudha, Zhao Ma, Krishna Garlapati, Ashish Sirasao
  • Patent number: 10387600
    Abstract: Reducing dynamic power consumption for a circuit can include analyzing, using a processor, a netlist specifying the circuit to determine a block of combinatorial circuitry in a first signal path with at least a threshold amount of switching activity and detecting, using the processor, a second signal path coupled to the block of combinatorial circuitry by a sequential circuit element. The second signal path has a delay that meets a target signal path requirement. Using the processor, the netlist can be modified by subdividing the block of combinatorial circuitry into at least a first portion and a second portion and moving one of the portions from the first signal path to the second signal path, wherein the moving separates the first portion from the second portion by the sequential circuit element.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: August 20, 2019
    Assignee: XILINX, INC.
    Inventors: Chaithanya Dudha, Krishna Garlapati
  • Patent number: 10366001
    Abstract: Disclosed approaches of processing a circuit design include determining a subset of addresses of a first RAM of the circuit design that are accessed more often than a frequency threshold. A specification of a second RAM is created for the subset of addresses. A decoder circuit is added to the circuit design. The decoder circuit is configured to enable the second RAM and disable the first RAM in response to an input address in the subset of addresses, and to enable the first RAM and disable the second RAM in response to an input address other than addresses in the subset of addresses.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: July 30, 2019
    Assignee: XILINX, INC.
    Inventors: Nithin Kumar Guggilla, Chaithanya Dudha, Krishna Garlapati, Chun Zhang, Fan Zhang, Anup Kumar Sultania
  • Publication number: 20180075172
    Abstract: Reducing dynamic power consumption for a circuit can include analyzing, using a processor, a netlist specifying the circuit to determine a block of combinatorial circuitry in a first signal path with at least a threshold amount of switching activity and detecting, using the processor, a second signal path coupled to the block of combinatorial circuitry by a sequential circuit element. The second signal path has a delay that meets a target signal path requirement. Using the processor, the netlist can be modified by subdividing the block of combinatorial circuitry into at least a first portion and a second portion and moving one of the portions from the first signal path to the second signal path, wherein the moving separates the first portion from the second portion by the sequential circuit element.
    Type: Application
    Filed: September 15, 2016
    Publication date: March 15, 2018
    Applicant: Xilinx, Inc.
    Inventors: Chaithanya Dudha, Krishna Garlapati
  • Patent number: 9460253
    Abstract: In an example, a method of processing a circuit design includes: determining a first partition in a description of the circuit design having a hierarchy of design objects, the first partition including at least one design object in the hierarchy of design objects; generating a signature for the first partition; querying a database with the signature of the first partition to identify a plurality of predefined implementations of the first partition; and generating an implementation of the circuit design for a target integrated circuit (IC) based on a selected predefined implementation of the plurality of predefined implementations for the first partition.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: October 4, 2016
    Assignee: XILINX, INC.
    Inventors: Elliott Delaye, Ashish Sirasao, Krishna Garlapati, Bing Tian
  • Patent number: 9268891
    Abstract: Compiling a circuit design includes receiving the circuit design specified in a hardware description language, detecting, using a processor, a slice of a vector within the circuit design, and determining that the slice is defined by a left slice boundary variable and a right slice boundary variable. A hardware description is generated from the circuit design using the processor by including a first shifter circuit receiving the left slice boundary variable as an input signal, a second shifter circuit receiving the right slice boundary variable as an input signal, a control signal generator coupled to the first and second shifter circuits, and an output stage. The output stage, responsive to a control signal dependent upon an output from the first shifter circuit and an output from second shifter circuit, generates an output signal including newly received values from a data signal only for bit locations of the output signal corresponding to the slice.
    Type: Grant
    Filed: November 6, 2014
    Date of Patent: February 23, 2016
    Assignee: XILINX, INC.
    Inventors: Krishna Garlapati, Elliott Delaye, Ashish Sirasao, Bing Tian
  • Patent number: 9235498
    Abstract: A circuit for enabling a modification of an input data stream is described. The circuit comprises a first plurality of registers coupled in series; an input register of the first plurality of registers coupled to receive the input data stream; an output register of the first plurality of registers positioned at an end of the first plurality of registers; and a control circuit enabling a data value which is independent of the input data stream to be generated as an output of the circuit at a predetermined time.
    Type: Grant
    Filed: June 3, 2013
    Date of Patent: January 12, 2016
    Assignee: XILINX, INC.
    Inventors: Jay Southard, Krishna Garlapati, Elliott Delaye, Ashish Sirasao, Bing Tian
  • Patent number: 8667436
    Abstract: The disclosure describes approaches for processing a circuit design. For each object of a plurality of objects of the circuit design, a respective key is generated as a function of a plurality of configuration parameter values of the object. Each object is renamed with a unique name that includes the key. A netlist of the circuit design is generated using the unique names and keys of the objects.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: March 4, 2014
    Assignee: Xilinx, Inc.
    Inventors: Krishna Garlapati, Elliot Delaye, Ashish Sirasao
  • Patent number: 6618835
    Abstract: One embodiment of the present invention identifies a circuit having a loop structure and a tri-state element. The circuit provides a circuit output. The loop structure contains at least a loop element in a feedback connection. The tri-state element receives first tri-state inputs. The circuit is transformed so that the tri-state element is moved across the loop structure to provide the circuit output.
    Type: Grant
    Filed: September 7, 2001
    Date of Patent: September 9, 2003
    Assignee: Synplicity, Inc.
    Inventors: Krishna Garlapati, Kenneth S. McElvain