Patents by Inventor Krishna K. Parat

Krishna K. Parat has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11043534
    Abstract: Various embodiments comprise apparatuses and methods, such as a memory stack having a continuous cell pillar. In various embodiments, the apparatus includes a source material, a buffer material, a select gate drain (SGD), and a memory stack arranged between the source material and the SGD. The memory stack comprises alternating levels of conductor materials and dielectric materials. A continuous channel-fill material forms a cell pillar that is continuous from the source material to at least a level corresponding to the SGD.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: June 22, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Fatma Arzum Simsek-Ege, Krishna K. Parat
  • Publication number: 20210174874
    Abstract: Apparatus and methods are disclosed, such as an apparatus that includes a string of charge storage devices associated with a pillar (e.g., of semiconductor material), a source gate device, and a source select device coupled between the source gate device and the string. Additional apparatus and methods are described.
    Type: Application
    Filed: September 21, 2020
    Publication date: June 10, 2021
    Inventors: Akira Goda, Shafqat Ahmed, Khaled Hasnat, Krishna K. Parat
  • Publication number: 20210117270
    Abstract: Error correction coding (ECC) mis-corrected reads, if undetected, result in silent data corruption of a non-volatile memory device. Overcoming ECC mis-corrected reads is based on a read signature of a result of reading a page in the non-volatile memory device. An ECC mis-correct logic counts the number of bits in the end-most buckets into which the bits of the result is divided. End-most buckets that are overpopulated or starved reveal a tell-tale read signature of an ECC mis-correct. The ECC mis-correct is likely to occur when the read reference voltage level used to read the page is shifted in one direction or another to an extreme amount that risks reading data from a different page. Detecting ECC mis-corrected reads can be used to overcome the ECC mis-corrects and mitigate silent data corruption.
    Type: Application
    Filed: December 24, 2020
    Publication date: April 22, 2021
    Inventors: Krishna K. PARAT, Ravi H. MOTWANI, Rohit S. SHENOY, Ali KHAKIFIROOZ
  • Publication number: 20210118508
    Abstract: Some embodiments include apparatuses and methods of forming such apparatuses. One of the apparatus includes first memory cells located in different levels in a first portion of the apparatus, second memory cells located in different levels in a second portion of the apparatus, a switch located in a third portion of the apparatus between the first and second portions, first and second control gates to access the first and second memory cells, an additional control gate located between the first and second control gates to control the switch, a first conductive structure having a thickness and extending perpendicular to the levels in the first portion of the apparatus, a first dielectric structure between the first conductive structure and charge-storage portions of the first memory cells, a second dielectric structure having a second thickness between the second conductive structure and a sidewall of the additional control gate, the second thickness being greater than the first thickness.
    Type: Application
    Filed: November 2, 2020
    Publication date: April 22, 2021
    Inventors: Benben Li, Akira Goda, Ramey M. Abdelrahaman, Ian C. Laboriante, Krishna K. Parat
  • Patent number: 10903219
    Abstract: Flash memory technology is disclosed. In one example, a flash memory cell can include a charge storage structure, a control gate laterally separated from the charge storage structure, and at least four dielectric layers disposed between the control gate and the charge storage structure. Associated systems and methods are also disclosed.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: January 26, 2021
    Assignee: Intel Corporation
    Inventors: Haitao Liu, Guangyu Huang, Krishna K. Parat, Shrotri B. Kunal, Srikant Jayanti
  • Patent number: 10847234
    Abstract: A technique for read or program verify (PV) operations for non-volatile memory is described. In one example, at the end of a program verify operation (e.g., during a program verify recovery phase), a number of wordlines near a selected wordline are ramped down one at a time. Ramping down wordlines near the selected wordline one at a time can significantly reduce the trapped charge in the channel, enabling lower program disturb rates and improved threshold voltage distributions. In one example, the same technique of ramping down wordlines near the selected wordline can be applied to a read operation.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: November 24, 2020
    Assignee: Intel Corporation
    Inventors: Han Zhao, Richard Fastow, Krishna K. Parat, Arun Thathachary, Narayanan Ramanan
  • Publication number: 20200350028
    Abstract: Reduction of program disturb degradation in a flash memory cell array is facilitated by selectively switching wordline voltage levels in a sequence that reduces the likelihood of trapping electrons in memory cell channels. During a program verify operation for a memory cell in a memory cell string, a flash memory system switches wordline voltage levels from high-to-low for interface wordlines, prior to switching wordline voltages from high-to-low for other wordlines in a memory cell string. Selectively switching wordlines in a sequence in the memory cell string enables electrons to migrate to ground or to a source voltage through upper and lower select gates.
    Type: Application
    Filed: April 17, 2020
    Publication date: November 5, 2020
    Applicant: Intel Corporation
    Inventors: HAN ZHAO, PRANAV KALAVADE, KRISHNA K. PARAT
  • Patent number: 10825831
    Abstract: Storage node configurations are described. A storage node (e.g., a floating gate or a charge trap layer of a three-dimensional (3D) NAND flash device) include a channel-facing surface with a radius of curvature. For example, a channel-facing surface of the storage node may be concave. A control gate-facing surface of the storage node may instead, or additionally, also include a radius of curvature. The radius of curvature of the channel-facing and/or control gate-facing surfaces of the storage node is less than or equal to the radius of the channel layer.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: November 3, 2020
    Assignee: Intel Corporation
    Inventors: Randy J. Koval, Henok T. Mebrahtu, Krishna K. Parat
  • Patent number: 10825523
    Abstract: Some embodiments include apparatuses and methods of forming such apparatuses. One of the apparatus includes first memory cells located in different levels in a first portion of the apparatus, second memory cells located in different levels in a second portion of the apparatus, a switch located in a third portion of the apparatus between the first and second portions, first and second control gates to access the first and second memory cells, an additional control gate located between the first and second control gates to control the switch, a first conductive structure having a thickness and extending perpendicular to the levels in the first portion of the apparatus, a first dielectric structure between the first conductive structure and charge-storage portions of the first memory cells, a second dielectric structure having a second thickness between the second conductive structure and a sidewall of the additional control gate, the second thickness being greater than the first thickness.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: November 3, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Benben Li, Akira Goda, Ramey M. Abdelrahaman, Ian C. Laboriante, Krishna K. Parat
  • Publication number: 20200342946
    Abstract: A technique for read or program verify (PV) operations for non-volatile memory is described. In one example, at the end of a program verify operation (e.g., during a program verify recovery phase), a number of wordlines near a selected wordline are ramped down one at a time. Ramping down wordlines near the selected wordline one at a time can significantly reduce the trapped charge in the channel, enabling lower program disturb rates and improved threshold voltage distributions. In one example, the same technique of ramping down wordlines near the selected wordline can be applied to a read operation.
    Type: Application
    Filed: April 26, 2019
    Publication date: October 29, 2020
    Inventors: Han ZHAO, Richard FASTOW, Krishna K. PARAT, Arun THATHACHARY, Narayanan RAMANAN
  • Patent number: 10796778
    Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. At least one of such apparatus can include a module configured to store information in a memory cell among memory cells and/or to determine a value of information stored in a memory cell among memory cells. The module can also be configured to apply a voltage having a positive value to the data line and/or a source to control a potential of the body. Other embodiments are described.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: October 6, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Han Zhao, Akira Goda, Krishna K. Parat, Aurelio Giancarlo Mauri, Haitao Liu, Toru Tanzawa, Shigekazu Yamada, Koji Sakui
  • Patent number: 10783967
    Abstract: Apparatus and methods are disclosed, such as an apparatus that includes a string of charge storage devices associated with a pillar (e.g., of semiconductor material), a source gate device, and a source select device coupled between the source gate device and the string. Additional apparatus and methods are described.
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: September 22, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Akira Goda, Shafqat Ahmed, Khaled Hasnat, Krishna K. Parat
  • Publication number: 20200243437
    Abstract: A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The stack has a primary portion and an end portion. At least some of the features extend farther in the horizontal direction in the end portion moving deeper into the stack in the end portion. Operative structures are formed vertically through the features in the primary portion and dummy structures are formed vertically through the features in the end portion. Horizontally elongated openings are formed through the features to form horizontally elongated and vertically overlapping lines from material of the features. The lines individually extend from the primary portion into the end portion, and individually laterally about sides of vertically extending portions of both the operative structures and the dummy structures.
    Type: Application
    Filed: April 16, 2020
    Publication date: July 30, 2020
    Applicant: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Roger W. Lindsay, Krishna K. Parat
  • Publication number: 20200234781
    Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. At least one of such apparatus can include a module configured to store information in a memory cell among memory cells and/or to determine a value of information stored in a memory cell among memory cells. The module can also be configured to apply a voltage having a positive value to the data line and/or a source to control a potential of the body. Other embodiments are described.
    Type: Application
    Filed: November 25, 2019
    Publication date: July 23, 2020
    Inventors: Han Zhao, Akira Goda, Krishna K. Parat, Aurelio Giancarlo Mauri, Haitao Liu, Toru Tanzawa, Shigekazu Yamada, Koji Sakui
  • Patent number: 10699790
    Abstract: Methods, and apparatuses to erase and or soft program a block of NAND memory may include performing an erase cycle on a block of NAND memory comprising two or more sub-blocks, verifying the two or more sub-blocks until a sub-block fails to verify, stopping the verification in response to the failed verify, performing another erase cycle on the block of NAND memory, and re-starting to verify the two or more sub-blocks at the sub-block that failed to verify.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: June 30, 2020
    Assignee: Intel Corporation
    Inventors: Krishna K. Parat, Pranav Kalavade, Koichi Kawai, Akira Goda
  • Patent number: 10658285
    Abstract: A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The stack has a primary portion and an end portion. At least some of the features extend farther in the horizontal direction in the end portion moving deeper into the stack in the end portion. Operative structures are formed vertically through the features in the primary portion and dummy structures are formed vertically through the features in the end portion. Horizontally elongated openings are formed through the features to form horizontally elongated and vertically overlapping lines from material of the features. The lines individually extend from the primary portion into the end portion, and individually laterally about sides of vertically extending portions of both the operative structures and the dummy structures.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: May 19, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Roger W. Lindsay, Krishna K. Parat
  • Patent number: 10658053
    Abstract: The inhibit voltage is a voltage applied to wordlines adjacent to a program wordline having a memory cell to write during the program operation. The inhibit voltage for a program operation can be ramped up during the program pulse. Instead of applying a constant high inhibit voltage that results in the initial boosted channel potential reducing drastically due to leakage, a system can start the inhibit voltage lower and ramp the inhibit voltage up during the program pulse. The ramping up can be a continuous ramp or in finite discrete steps during the program pulse. Such ramping of inhibit voltage can provide better tradeoff between program disturb and inhibit disturb.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: May 19, 2020
    Assignee: Intel Corporation
    Inventors: Shantanu R. Rajwade, Pranav Kalavade, Neal R. Mielke, Krishna K. Parat, Shyam Sunder Raghunathan
  • Publication number: 20200144331
    Abstract: Various embodiments comprise apparatuses and methods, such as a memory stack having a continuous cell pillar. In various embodiments, the apparatus includes a source material, a buffer material, a select gate drain (SGD), and a memory stack arranged between the source material and the SGD. The memory stack comprises alternating levels of conductor materials and dielectric materials. A continuous channel-fill material forms a cell pillar that is continuous from the source material to at least a level corresponding to the SGD.
    Type: Application
    Filed: January 6, 2020
    Publication date: May 7, 2020
    Inventors: Fatma Arzum Simsek-Ege, Krishna K. Parat
  • Publication number: 20200135748
    Abstract: Some embodiments include apparatuses and methods having a source material, a dielectric material over the source material, a select gate material over the dielectric material, a memory cell stack over the select gate material, a conductive plug located in an opening of the dielectric material and contacting a portion of the source material, and a channel material extending through the memory cell stack and the select gate material and contacting the conductive plug.
    Type: Application
    Filed: December 23, 2019
    Publication date: April 30, 2020
    Inventors: Fatma Arzum Simsek-Ege, Krishna K. Parat, Luan C. Tran, Meng-Wei Kuo, Yushi Hu
  • Patent number: 10629271
    Abstract: Reduction of program disturb degradation in a flash memory cell array is facilitated by selectively switching wordline voltage levels in a sequence that reduces the likelihood of trapping electrons in memory cell channels. During a program verify operation for a memory cell in a memory cell string, a flash memory system switches wordline voltage levels from high-to-low for interface wordlines, prior to switching wordline voltages from high-to-low for other wordlines in a memory cell string. Selectively switching wordlines in a sequence in the memory cell string enables electrons to migrate to ground or to a source voltage through upper and lower select gates.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: April 21, 2020
    Assignee: Intel Corporation
    Inventors: Han Zhao, Pranav Kalavade, Krishna K. Parat