Patents by Inventor Krishna P. Pande

Krishna P. Pande has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7969374
    Abstract: A multipath enhancer is disclosed ias including more than one antenna. At least one of a receiver and a transmitter is coupled to the more than one antenna. A selectively reflective surface is adjacent the more than one antenna. A controller is configured to alter the reflectivity of the selectively reflective surface.
    Type: Grant
    Filed: July 2, 2007
    Date of Patent: June 28, 2011
    Assignee: Rockwell Collins, Inc.
    Inventors: John Thommana, Krishna P. Pande, Lizy Paul
  • Patent number: 5416971
    Abstract: A monolithic gallium arsenide (GaAs) phased array using integrated gold (Au) posts for interconnecting multiple substrate layers. The phased array includes a GaAs substrate having transmit/receive modules fabricated on one side and radiating elements etched on the backside of the same substrate. The conductive gold posts are integrated on the same side with the transmit/receive modules and interconnect the transmit/receive modules with a distribution network which is printed on a second substrate. Gold posts are also used to interconnect DC bias and control lines of the two substrates.
    Type: Grant
    Filed: July 28, 1993
    Date of Patent: May 23, 1995
    Inventors: Gamal M. Hegazi, Krishna P. Pande, Amin Ezzeddine, Robert Sorbello, Bernard Geller
  • Patent number: 5262794
    Abstract: A monolithic gallium arsenide (GaAs) phased array using integrated gold (Au) posts for interconnecting multiple substrate layers. The phased array includes a GaAs substrate having transmit/receive modules fabricated on one side and radiating elements etched on the backside of the same substrate. The conductive gold posts are integrated on the same side with the transmit/receive modules and interconnect the transmit/receive modules with a distribution network which is printed on a second substrate. Gold posts are also used to interconnect DC bias and control lines of the two substrates.
    Type: Grant
    Filed: July 18, 1991
    Date of Patent: November 16, 1993
    Assignee: Communications Satellite Corporation
    Inventors: Gamal M. Hegazi, Krishna P. Pande, Amin Ezzeddine, Robert Sorbello, Bernard Geller
  • Patent number: 4611388
    Abstract: A heterojunction bipolar transistor having an n- type epitaxial indium phosphide collector layer grown on a semi-insulating indium phosphide substrate with an n+ buried layer, a p- type indium phosphide base and an epitaxial, n- type boron phosphide wide gap emitter. The p- type base region is formed by ion implantation of magnesium ions into the collector layer. The transistor is applicable to millimeter wave applications due to the high electron mobility in the indium phosphide base. The wide gaps of both the boron phosphide (2.2 eV) and indium phosphide (1.34 eV) permit operation up to 350.degree. C. The transistor is easily processed using metal organic-chemical vapor deposition (MO-CVD) and standard microelectronic techniques.
    Type: Grant
    Filed: April 15, 1985
    Date of Patent: September 16, 1986
    Assignee: Allied Corporation
    Inventor: Krishna P. Pande
  • Patent number: 4529996
    Abstract: A heterojunction bipolar transistor having an n- type epitaxial indium phosphide collector layer grown on a semi-insulating indium phosphide substrate with an n+ buried layer, a p- type indium phosphide base and an epitaxial, n- type boron phosphide wide gap emitter. The p- type base region is formed by ion implantation of magnesium ions into the collector layer. The transistor is applicable to millimeter wave applications due to the high electron mobility in the indium phosphide base. The wide gaps of both the boron phosphide (2.2 eV) and indium phosphide (1.34 eV) permit operation up to 350.degree. C. The transistor is easily processed using metal organic-chemical vapor deposition (MO-CVD) and standard microelectronic techniques.
    Type: Grant
    Filed: April 14, 1983
    Date of Patent: July 16, 1985
    Assignee: Allied Coporation
    Inventor: Krishna P. Pande