Patents by Inventor Krishna Thakur

Krishna Thakur has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240088879
    Abstract: A multiphase digital frequency synthesizer including a multiphase ring oscillator that provides phased clock signals, a clock divider that divides a phased clock signal by an integer value and a carry value to provide a divided clock signal, positive select circuitry that determines and updates a positive select value with accumulation and a modulo function based on a fractional division factor updated with successive cycles of the divided clock signal, carry circuitry that determines the carry value based on a number of the phased clock signals, positive multiplex circuitry that selects from among the phased clock signal using the positive select value for providing a positive multiplexed clock signal, and fractional phase addition circuitry that provides a first output clock signal based on a selected phased clock signal, the divided clock signal, and the positive multiplexed clock signal. Similar negative select circuitry and duty cycle correction circuitry may be included.
    Type: Application
    Filed: April 6, 2023
    Publication date: March 14, 2024
    Inventors: Ravi Kumar, Gaurav Agrawal, Deependra Kumar Jain, Krishna Thakur
  • Patent number: 11876486
    Abstract: A low power crystal oscillator is provided. The crystal oscillator includes a gain stage circuit having a first gain stage input coupled at a first oscillator terminal and configured to receive a first oscillator signal of a crystal. A first bias circuit is configured to generate a first bias voltage based on the first oscillator signal. A reference circuit is configured to generate a reference current based on the first bias voltage. A comparator circuit is configured to generate a clock signal based on the first oscillator signal and the first bias voltage. The comparator circuit includes a second bias circuit configured to generate a second bias voltage. The gain stage circuit includes a second gain stage input coupled to receive the second bias voltage.
    Type: Grant
    Filed: January 16, 2023
    Date of Patent: January 16, 2024
    Assignee: NXP B.V.
    Inventors: Siyaram Sahu, Anand Kumar Sinha, Ateet Omer, Krishna Thakur
  • Patent number: 11646743
    Abstract: A digital phase-locked loop (PLL) includes a time-to-digital converter (TDC) and a digitally controlled oscillator (DCO). The DCO generates a PLL clock signal and various sampling clock signals that are mesochronous. The TDC samples a phase difference between a reference clock signal and a frequency-divided version of the PLL clock signal based on the sampling clock signals and various enable signals. The enable signals are generated based on a calibration of the digital PLL. Each enable signal is associated with a sampling clock signal and indicates whether the associated sampling clock signal is to be utilized for sampling the phase difference. Further, the TDC generates control data indicative of the sampled phase difference. The DCO generates the PLL clock signal and the sampling clock signals based on the control data until the digital PLL is in a phase-locked state.
    Type: Grant
    Filed: March 9, 2022
    Date of Patent: May 9, 2023
    Assignee: NXP USA, Inc.
    Inventors: Pawan Sabharwal, Anand Kumar Sinha, Krishna Thakur, Deependra Kumar Jain
  • Patent number: 11601130
    Abstract: An initialization circuit of a delay locked loop (DLL) includes a sense circuit and a control circuit. The sense circuit receives an enable signal, a reference clock signal, and various delayed reference clock signals, and outputs another enable signal. The control circuit receives the two enable signals and outputs and provides a control signal to a loop filter of the DLL to control a delay value associated with the DLL. The control signal is provided to the loop filter such that the delay value associated with the DLL equals a predetermined delay value for a predetermined time duration. Further, after a lapse of the predetermined time duration, the delay value associated with the DLL increases until a difference between a time period of the reference clock signal and the delay value equals a threshold value.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: March 7, 2023
    Assignee: NXP B.V.
    Inventors: Gaurav Agrawal, Deependra Kumar Jain, Krishna Thakur
  • Patent number: 11581850
    Abstract: An enabling system that includes a controller and processing circuitry, is configured to enable an external oscillator that operates in one of single-ended, differential, and crystal modes. To enable the external oscillator, the controller is configured to detect a mode of operation of the external oscillator, and the processing circuitry is configured to operate in the detected mode. The controller detects the mode of operation of the external oscillator by sequentially initializing the processing circuitry to operate in the single-ended, differential, and crystal modes, and determining whether the current operating mode of the processing circuitry is same as the mode of operation of the external oscillator based on a clock signal outputted by the processing circuitry during the corresponding mode.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: February 14, 2023
    Assignee: NXP USA, INC.
    Inventors: Atul Dahiya, Krishna Thakur, Deependra Kumar Jain
  • Publication number: 20220416796
    Abstract: An initialization circuit of a delay locked loop (DLL) includes a sense circuit and a control circuit. The sense circuit receives an enable signal, a reference clock signal, and various delayed reference clock signals, and outputs another enable signal. The control circuit receives the two enable signals and outputs and provides a control signal to a loop filter of the DLL to control a delay value associated with the DLL. The control signal is provided to the loop filter such that the delay value associated with the DLL equals a predetermined delay value for a predetermined time duration. Further, after a lapse of the predetermined time duration, the delay value associated with the DLL increases until a difference between a time period of the reference clock signal and the delay value equals a threshold value.
    Type: Application
    Filed: June 23, 2021
    Publication date: December 29, 2022
    Inventors: Gaurav Agrawal, Deependra Kumar Jain, Krishna Thakur
  • Publication number: 20220166380
    Abstract: An enabling system that includes a controller and processing circuitry, is configured to enable an external oscillator that operates in one of single-ended, differential, and crystal modes. To enable the external oscillator, the controller is configured to detect a mode of operation of the external oscillator, and the processing circuitry is configured to operate in the detected mode. The controller detects the mode of operation of the external oscillator by sequentially initializing the processing circuitry to operate in the single-ended, differential, and crystal modes, and determining whether the current operating mode of the processing circuitry is same as the mode of operation of the external oscillator based on a clock signal outputted by the processing circuitry during the corresponding mode.
    Type: Application
    Filed: November 24, 2020
    Publication date: May 26, 2022
    Inventors: Atul Dahiya, Krishna Thakur, Deependra Kumar Jain
  • Patent number: 11075638
    Abstract: A calibration system of a digital phase locked loop (DPLL) includes a calibration circuit and a digitally controlled oscillator (DCO). The calibration circuit is configured to receive an input signal and a feedback signal, and generate a digital signal, based on a frequency of the input signal, a frequency of the feedback signal, and an input bias code. The DCO is configured to receive the input bias code and the digital signal, and generate a bias signal based on the input bias code. The DCO is further configured to generate an analog signal based on the bias signal and the digital signal, and generate the feedback signal such that the frequency of the feedback signal is based on an amplitude of the analog signal.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: July 27, 2021
    Assignee: NXP USA, INC.
    Inventors: Anand Kumar Sinha, Krishna Thakur, Pawan Sabharwal
  • Patent number: 10263627
    Abstract: A delay-locked loop (DLL) includes a delay line configured to receive a reference clock signal and a control signal, and generate a first plurality of clock signals. Each clock signal of the first plurality is configured to have a different phase delay relative to the reference clock signal. A phase frequency detector is coupled to the delay circuit and is configured to receive a first clock signal and a second clock signal of the first plurality, and generate up and down control signals. A charge pump is coupled to receive the up and down control signals and generates a charge pump current based on the up and down control signals. An output of the charge pump is coupled to the delay line at a voltage control node. An initialization circuit is coupled to the voltage control node and is configured to generate an initialization voltage based on the reference clock signal frequency.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: April 16, 2019
    Assignee: NXP USA, INC.
    Inventors: Deependra Jain, Krishna Thakur, Gaurav Agrawal
  • Patent number: 9419629
    Abstract: A delay-locked loop (DLL) has a fractional phase frequency (PF) detector that reduces false locking and harmonic locking. The PF detector has a trunk, an upper branch, a lower branch, and a logic module. A delay line provides the PF detector a set of fractional phase-delayed clock signals that are used to prime and/or activate corresponding flip-flops of the trunk, upper branch, and lower branch in a sequence. The use of flip-flops in the lower branch activated by different fractional phase-delayed clock signals avoids false locking and harmonic locking over a wider range of initial delay magnitudes than conventional DLLs.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: August 16, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Gaurav Agrawal, Deependra K. Jain, Krishna Thakur
  • Patent number: 9362894
    Abstract: A clock generator includes a diagnostic circuit that includes first and second muxes, first and second comparators, a logic gate, and a counter. The first mux receives first and second voltage signals and outputs a first intermediate signal based on a control signal. The second mux receives third and fourth voltage signals and outputs a second intermediate signal based on the control signal. The first and second comparators compare the intermediate signals with a first signal that is indicative of a DC value of the clock signal for generating first and second comparison signals. The logic gate receives the first and second intermediate signals and generates a control signal. The counter receives the clock signal and the control signal and generates a clock ready signal that is indicative of stability and quality of the clock signal.
    Type: Grant
    Filed: May 4, 2015
    Date of Patent: June 7, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Ateet Omer, Deependra K. Jain, Anand Kumar Sinha, Krishna Thakur
  • Patent number: 9337818
    Abstract: A buffer circuit includes an inverter and a level-shifter. The inverter receives a first oscillating signal at a first voltage level and generates an inverted version of the first oscillating signal at a second voltage level. The level-shifter receives a second oscillating signal at a third voltage level, which has a phase difference from the first oscillating signal, and the inverted first oscillating signal, and generates a buffer output signal at a fourth voltage level.
    Type: Grant
    Filed: August 23, 2015
    Date of Patent: May 10, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Krishna Thakur, Deependra K. Jain, Devesh P. Singh, Anand Kumar Sinha, Avinash Chandra Tripathi
  • Patent number: 9331698
    Abstract: A level shifter circuit for level shifting voltages of signals crossing multiple circuit domains includes an input stage and a driver stage. The input stage receives an oscillating signal generated by a ring oscillator and generates an inverted oscillating signal. The differential oscillating signals are provided to the driver stage, which level shifts a voltage level of the oscillating signal to a level of a supply voltage of the ring oscillator.
    Type: Grant
    Filed: January 2, 2014
    Date of Patent: May 3, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Deependra K. Jain, Krishna Thakur
  • Patent number: 9252791
    Abstract: A phase locked loop (PLL) system generates an oscillator signal by providing a fixed control voltage to a programmable voltage to current converter having switch selection inputs and a variable current output. Logic values are provided to the switch selection inputs to adjust a control current at the variable current output and a frequency of the oscillator signal is adjusted based on the control current. The logic values are fixed when a first condition is reached, which is based on the frequency of the oscillator signal, a division factor, and an input reference signal frequency. The fixed control voltage provided to the programmable voltage to current converter is then replaced with a charge pump control voltage based on an error signal. The error signal is based on a comparison of the input reference signal frequency and a fraction of the oscillating frequency.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: February 2, 2016
    Assignee: FREESCALE SEMICONDUCTOR,INC.
    Inventors: Anand Kumar Sinha, Deependra K. Jain, Krishna Thakur
  • Publication number: 20150188543
    Abstract: A level shifter circuit for level shifting voltages of signals crossing multiple circuit domains includes an input stage and a driver stage. The input stage receives an oscillating signal generated by a ring oscillator and generates an inverted oscillating signal. The differential oscillating signals are provided to the driver stage, which level shifts a voltage level of the oscillating signal to a level of a supply voltage of the ring oscillator.
    Type: Application
    Filed: January 2, 2014
    Publication date: July 2, 2015
    Inventors: Deependra K. Jain, Krishna Thakur
  • Patent number: 8432200
    Abstract: A phase-locked loop (PLL) generates an oscillator signal based on an input reference signal. A voltage-to-current converter converts a control voltage to a first current and a current-controlled oscillator generates the oscillator signal based on the first current. A dual charge pump circuit generates first and second charge pump currents having a predetermined ratio based on fractions of the calibration current and the first current and an error (feedback) signal. An active loop filter generates the control voltage based on the first and second charge pump currents and includes a transconductance stage having a transconductance that varies with the variation in a third current. The variation in the transconductance causes the second charge pump current to vary, which in turn adjusts the predetermined ratio between the first and second charge pump currents.
    Type: Grant
    Filed: January 5, 2012
    Date of Patent: April 30, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Krishna Thakur
  • Patent number: 8378725
    Abstract: A phase-locked loop (PLL) generates an oscillator signal based on an input reference signal. A voltage-to-current converter converts a control voltage to a first current. A current-controlled oscillator generates the oscillator signal based on the first current. A dual charge pump circuit generates first and second charge pump currents having a predetermined ratio, based on a second current generated by a current mirror circuit and an error (feedback) signal. An active loop filter generates the control voltage based on the first and second charge pump currents. The active loop filter includes an input capacitance that varies with a variation in the predetermined ratio of the charge pump currents. The active loop filter also includes a transconductance stage having a transconductance that varies based on a third current generated by a current mirror circuit. The PLL bandwidth is independent of PVT variations and dependent only on the frequency of the input reference signal.
    Type: Grant
    Filed: March 14, 2011
    Date of Patent: February 19, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Krishna Thakur, Deependra K. Jain, Vinod K. Jain
  • Publication number: 20120235718
    Abstract: A phase-locked loop (PLL) generates an oscillator signal based on an input reference signal. A voltage-to-current converter converts a control voltage to a first current. A current-controlled oscillator generates the oscillator signal based on the first current. A dual charge pump circuit generates first and second charge pump currents having a predetermined ratio, based on a second current generated by a current mirror circuit and an error (feedback) signal. An active loop filter generates the control voltage based on the first and second charge pump currents. The active loop filter includes an input capacitance that varies with a variation in the predetermined ratio of the charge pump currents. The active loop filter also includes a transconductance stage having a transconductance that varies based on a third current generated by a current mirror circuit. The PLL bandwidth is independent of PVT variations and dependent only on the frequency of the input reference signal.
    Type: Application
    Filed: March 14, 2011
    Publication date: September 20, 2012
    Applicant: FREESCALE SEMICONDUCTOR, INC
    Inventors: Krishna THAKUR, Deependra K. JAIN, Vinod K. JAIN
  • Patent number: 8248130
    Abstract: A duty cycle correction circuit for correcting the duty cycle of a clock signal generated by a clock generator includes a complementary buffer chain, level shifter circuits and a self-bias circuit. A clock signal with a distorted duty cycle and its complement are provided to the level shifter circuits. The level shifter circuits reduce the magnitude of voltage of the clock signal and the complement and generate level shifted signals. The level shifted signals are provided to a differential amplifier that generates a control signal indicating the magnitude of distortion in the duty cycle. The control signal is used to correct the duty cycle of the clock signal. The self-bias circuit is used to bias the differential amplifier.
    Type: Grant
    Filed: May 25, 2010
    Date of Patent: August 21, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Vinod Jain, Deependra K. Jain, Krishna Thakur, Avinish Chandra Tripathi, Sanjay Kumar Wadhwa
  • Patent number: 8093929
    Abstract: A programmable digital clock signal frequency divider module has a module clock input, module clock output, a scaling factor input, two programming inputs, and a tertiary input. A primary divider module with a primary divider module output and a clock input are coupled to the module clock input. A secondary divider module includes a multiplexer and a divide by two latch with a latch clock input coupled to the primary divider module output. In operation, logic values applied to the scaling factor input, and the programming inputs, result in the primary divider module processing a first sequence of cycles of a primary digital clock signal into a first base clock signal and processing a subsequent second sequence of cycles into a second base clock signal. The first base clock signal and the second base clock signal provide a sequence of clock pulses to the secondary divider module.
    Type: Grant
    Filed: March 2, 2010
    Date of Patent: January 10, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Ankesh Jain, Deependra Jain, Krishna Thakur