Patents by Inventor Krishna Vasanth VALAVALA

Krishna Vasanth VALAVALA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240063120
    Abstract: Embodiments of a microelectronic assembly comprise: a plurality of layers of integrated circuit (IC) dies, each layer coupled to adjacent layers by first interconnects having a pitch of less than 10 micrometers between adjacent first interconnects; an end layer in the plurality of layers proximate to a first side of the plurality of layers comprises a dielectric material around IC dies in the end layer and a through-dielectric via (TDV) in the dielectric material of the end layer; a support structure coupled to the first side of the plurality of layers, the support structure comprising a structurally stiff base with conductive traces proximate to the end layer, the conductive traces coupled to the end layer by second interconnects; and a package substrate coupled to a second side of the plurality of layers, the second side being opposite to the first side.
    Type: Application
    Filed: August 19, 2022
    Publication date: February 22, 2024
    Applicant: Intel Corporation
    Inventors: Adel A. Elsherbini, Shawna M. Liff, Debendra Mallik, Christopher M. Pelto, Kimin Jun, Johanna M. Swan, Lei Jiang, Feras Eid, Krishna Vasanth Valavala, Henning Braunisch, Patrick Morrow, William J. Lambert
  • Publication number: 20240063183
    Abstract: Embodiments of a microelectronic assembly comprise: a plurality of layers of monolithic wafers and disaggregated integrated circuit (IC) dies, adjacent layers being coupled together by first interconnects having a pitch less than 10 micrometers between adjacent first interconnects, the disaggregated IC dies arranged with portions of the monolithic wafers into modular sub-assemblies; and a package substrate coupled to the modular sub-assemblies by second interconnects having a pitch greater than 10 micrometers between adjacent second interconnects. The disaggregated IC dies are surrounded laterally by a dielectric material, and the disaggregated IC dies are arranged with portions of the monolithic wafers such that a voltage regulator circuit in a first layer of the plurality of layers, a compute circuit in a second layer of the plurality of layers, and a memory circuit in a third layer of the plurality of layers are conductively coupled together in an intra-modular power delivery circuitry.
    Type: Application
    Filed: August 19, 2022
    Publication date: February 22, 2024
    Applicant: Intel Corporation
    Inventors: Adel A. Elsherbini, Kaladhar Radhakrishnan, Anne Augustine, Beomseok Choi, Kimin Jun, Omkar G. Karhade, Shawna M. Liff, Julien Sebot, Johanna M. Swan, Krishna Vasanth Valavala
  • Publication number: 20240061194
    Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include an interconnect die in a first layer surrounded by a dielectric material; a processor integrated circuit (processor IC) and an integrated circuit (IC) in a second layer, the second layer on the first layer, wherein the interconnect die is electrically coupled to the processor IC and the IC by first interconnects having a pitch of less than 10 microns between adjacent first interconnects; a photonic integrated circuit (PIC) and a substrate in a third layer, the third layer on the second layer, wherein the PIC has an active surface, and wherein the active surface of the PIC is coupled to the IC by second interconnects having a pitch of less than 10 microns between adjacent second interconnects; and a fiber connector optically coupled to the active surface of the PIC.
    Type: Application
    Filed: August 19, 2022
    Publication date: February 22, 2024
    Applicant: Intel Corporation
    Inventors: Adel A. Elsherbini, David Hui, Haris Khan Niazi, Wenhao Li, Bhaskar Jyoti Krishnatreya, Henning Braunisch, Shawna M. Liff, Jiraporn Seangatith, Johanna M. Swan, Krishna Vasanth Valavala, Xavier Francois Brun, Feras Eid
  • Publication number: 20240063076
    Abstract: Microelectronic devices, assemblies, and systems include a multichip composite device having one or more integrated circuit dies bonded to a base die, a conformal thermal heat spreading layer on the top and sidewalls of the integrated circuit dies, and an inorganic dielectric material on a portion of the conformal thermal heat spreading layer, laterally adjacent the integrated circuit dies, and over the base die. The conformal thermal heat spreading layer includes a high thermal conductivity material to provide a thermal pathway for the integrated circuit dies during operation.
    Type: Application
    Filed: August 19, 2022
    Publication date: February 22, 2024
    Applicant: Intel Corporation
    Inventors: Mohammad Enamul Kabir, Bhaskar Jyoti Krishnatreya, Kimin Jun, Adel Elsherbini, Tushar Talukdar, Feras Eid, Debendra Mallik, Krishna Vasanth Valavala, Xavier Brun
  • Publication number: 20240063091
    Abstract: Microelectronic devices, assemblies, and systems include a multichip composite device having one or more chiplets bonded to a base die and an inorganic dielectric material adjacent the chiplets and over the base die. The multichip composite device is coupled to a structural member that is made of or includes a heat conducting material, or has integrated fluidic cooling channels to conduct heat from the chiplets and the base die.
    Type: Application
    Filed: August 19, 2022
    Publication date: February 22, 2024
    Applicant: Intel Corporation
    Inventors: Adel Elsherbini, Feras Eid, Scot Kellar, Yoshihiro Tomita, Rajiv Mongia, Kimin Jun, Shawna Liff, Wenhao Li, Johanna Swan, Bhaskar Jyoti Krishnatreya, Debendra Mallik, Krishna Vasanth Valavala, Lei Jiang, Xavier Brun, Mohammad Enamul Kabir, Haris Khan Niazi, Jiraporn Seangatith, Thomas Sounart
  • Publication number: 20240063179
    Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a dielectric layer having one or more conductive traces and a surface; a microelectronic subassembly on the surface of the dielectric layer, the microelectronic subassembly including a first die and a through-dielectric via (TDV) surrounded by a dielectric material, wherein the first die is at the surface of the dielectric layer; a second die and a third die on the first die and electrically coupled to the first die by interconnects having a pitch of less than 10 microns, and wherein the TDV is electrically coupled at a first end to the dielectric layer and at an opposing second end to the second die; and a substrate on and coupled to the second and third dies; and an insulating material on the surface of the dielectric layer and around the microelectronic subassembly.
    Type: Application
    Filed: August 19, 2022
    Publication date: February 22, 2024
    Applicant: Intel Corporation
    Inventors: Adel A. Elsherbini, Krishna Vasanth Valavala, Kimin Jun, Shawna M. Liff, Johanna M. Swan, Debendra Mallik, Feras Eid, Xavier Francois Brun, Bhaskar Jyoti Krishnatreya
  • Publication number: 20240063089
    Abstract: Microelectronic devices, assemblies, and systems include a multichip composite device having one or more integrated circuit dies bonded to a base die and an inorganic dielectric material adjacent the integrated circuit dies and over the base die. The multichip composite device includes a dummy die, dummy vias, or integrated fluidic cooling channels laterally adjacent the integrated circuit dies to conduct heat from the base die.
    Type: Application
    Filed: August 19, 2022
    Publication date: February 22, 2024
    Applicant: Intel Corporation
    Inventors: Adel Elsherbini, Wenhao Li, Bhaskar Jyoti Krishnatreya, Debendra Mallik, Krishna Vasanth Valavala, Lei Jiang, Yoshihiro Tomita, Omkar Karhade, Haris Khan Niazi, Tushar Talukdar, Mohammad Enamul Kabir, Xavier Brun, Feras Eid
  • Publication number: 20230290706
    Abstract: A surplus liquid reservoir attached to a vapor chamber integrated heat spreader (IHS) and placed near a heat source on a heterogenous die. The vapor chamber integrated heat spreader (IHS) includes a main heat transfer portion that encloses a vapor channel, a first wick material, and a first working fluid. The surplus liquid reservoir is provided by a reservoir leg mechanically coupled, on a first side, to the main heat transfer portion, the reservoir leg has a reservoir portion with a second working fluid and second wick material that is in contact with the first wick material. The surplus liquid reservoir can either support a PL2 that is higher than a given vapor chamber Qmax for a significantly long time or increase the PL2 value to a significantly higher value.
    Type: Application
    Filed: March 11, 2022
    Publication date: September 14, 2023
    Applicant: Intel Corporation
    Inventors: Gaurav Patankar, Shankar Devasenathipathy, Krishna Vasanth Valavala
  • Patent number: 11756856
    Abstract: Embodiments include a microelectronic device package structure having a first die on the substrate. One or more additional dice are on the first die, and a thermal electric cooler (TEC) is on the first die adjacent at least one of the one or more additional dice. A dummy die is on the TEC, wherein the dummy die is thermally coupled to the first die.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: September 12, 2023
    Assignee: Intel Corporation
    Inventors: Krishna Vasanth Valavala, Ravindranath Mahajan, Chandra Mohan Jha, Kelly Lofgreen, Weihua Tang
  • Patent number: 11694942
    Abstract: An integrated circuit (IC) package comprising an IC die, the IC die having a first surface and an opposing second surface. The IC die comprises a semiconductor material. The first surface comprises an active layer. A thermoelectric cooler (TEC) comprising a thermoelectric material is embedded within the IC die between the first surface and the second surface and adjacent to the active layer. The TEC has an annular shape that is substantially parallel to the first and second surfaces of the IC die. The thermoelectric material is confined between an outer sidewall along an outer perimeter of the TEC and an inner sidewall along an inner perimeter of the TEC. The outer and inner sidewalls are substantially orthogonal to the first and second surfaces of the IC die.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: July 4, 2023
    Assignee: Intel Corporation
    Inventors: Kelly Lofgreen, Chandra Mohan Jha, Krishna Vasanth Valavala
  • Patent number: 11664293
    Abstract: Embodiments include a semiconductor package with a thermoelectric cooler (TEC), a method to form such semiconductor package, and a semiconductor packaged system. The semiconductor package includes a die with a plurality of backend layers on a package substrate. The backend layers couple the die to the package substrate. The semiconductor package includes the TEC in the backend layers of the die. The TEC includes a plurality of N-type layers, a plurality of P-type layers, and first and second conductive layers. The first conductive layer is directly coupled to outer regions of bottom surfaces of the N-type and P-type layers, and the second conductive layer is directly coupled to inner regions of top surfaces of the N-type and P-type layers. The first conductive layer has a width greater than a width of the second conductive layer. The N-type and P-type layers are directly disposed between the first and second conductive layers.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: May 30, 2023
    Assignee: Intel Corporation
    Inventors: Krishna Vasanth Valavala, Ravindranath V. Mahajan, Chandra Mohan Jha
  • Patent number: 11658095
    Abstract: An IC package, comprising a first IC component comprising a first interconnect on a first surface thereof; a second IC component comprising a second interconnect on a second surface thereof. The second component is above the first component, and the second surface is opposite the first surface. A thermoelectric cooling (TEC) device is between the first surface and the second surface. The TEC device is electrically coupled to the first interconnect and to the second interconnect.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: May 23, 2023
    Assignee: Intel Corporation
    Inventors: Kelly Lofgreen, Chandra Mohan Jha, Krishna Vasanth Valavala
  • Publication number: 20230100576
    Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques directed to bridges having a glass core, where the bridges may include one or more thick traces and one or more thin traces, where the thin traces are layered closer to a surface of the glass core, and the thick traces are layered further away from the glass core. During operation, the thin traces may be used to transmit signals between the coupled dies, and the thick traces may be used to transmit power between the coupled dies. During manufacture, the rigidity and highly planner surface of the glass core may enable thinner traces closer to the surface of the glass core to be placed with greater precision resulting in increased overall quality and robustness of transmitted signals. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 17, 2021
    Publication date: March 30, 2023
    Inventors: Andrew COLLINS, Srinivas V. PIETAMBARAM, Jianyong XIE, Krishna Vasanth VALAVALA
  • Publication number: 20230081139
    Abstract: An example microelectronic assembly includes a substrate, a bridge die over the substrate, and a die stack between the substrate and the bridge die, the die stack including a logic die and at least one memory die, where the logic die is between the at least one memory die and the bridge die.
    Type: Application
    Filed: September 15, 2021
    Publication date: March 16, 2023
    Applicant: Intel Corporation
    Inventors: Krishna Vasanth Valavala, Chandra Mohan Jha, Andrew Paul Collins, Omkar G. Karhade
  • Patent number: 11462457
    Abstract: Embodiments herein relate to systems, apparatuses, processing, and techniques related to a first heat-conducting plate to be thermally coupled to a first heat source, a thermoelectric cooler (TEC) thermally coupled to the first plate, a second heat-conducting plate thermally coupled to the TEC and to be thermally coupled to a second heat source where the TEC is to at least partially thermally isolate the first plate from the second plate to reduce heat transfer from the first plate to the second plate.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: October 4, 2022
    Assignee: Intel Corporation
    Inventors: Krishna Vasanth Valavala, Kelly Lofgreen, Chandra-Mohan Jha
  • Publication number: 20210125897
    Abstract: Embodiments include a semiconductor package with a thermoelectric cooler (TEC), a method to form such semiconductor package, and a semiconductor packaged system. The semiconductor package includes a die with a plurality of backend layers on a package substrate. The backend layers couple the die to the package substrate. The semiconductor package includes the TEC in the backend layers of the die. The TEC includes a plurality of N-type layers, a plurality of P-type layers, and first and second conductive layers. The first conductive layer is directly coupled to outer regions of bottom surfaces of the N-type and P-type layers, and the second conductive layer is directly coupled to inner regions of top surfaces of the N-type and P-type layers. The first conductive layer has a width greater than a width of the second conductive layer. The N-type and P-type layers are directly disposed between the first and second conductive layers.
    Type: Application
    Filed: October 28, 2019
    Publication date: April 29, 2021
    Inventors: Krishna Vasanth VALAVALA, Ravindranath V. MAHAJAN, Chandra Mohan JHA
  • Publication number: 20200312741
    Abstract: An IC package comprising a substrate comprising a dielectric, an IC device coupled to the substrate; and a thermoelectric cooling (TEC) device adjacent to the IC device and coupled to the substrate. A thermal trace extends laterally on or within the dielectric between the TEC device to the IC device, and the thermal trace is coupled to the TEC device and the IC device.
    Type: Application
    Filed: March 25, 2019
    Publication date: October 1, 2020
    Applicant: Intel Corporation
    Inventors: Zhimin Wan, Krishna Vasanth Valavala, Chandra Mohan Jha, Shankar Devasenathipathy
  • Publication number: 20200312742
    Abstract: An IC package, comprising a first IC component comprising a first interconnect on a first surface thereof; a second IC component comprising a second interconnect on a second surface thereof. The second component is above the first component, and the second surface is opposite the first surface. A thermoelectric cooling (TEC) device is between the first surface and the second surface. The TEC device is electrically coupled to the first interconnect and to the second interconnect.
    Type: Application
    Filed: March 29, 2019
    Publication date: October 1, 2020
    Inventors: Kelly Lofgreen, Chandra Mohan Jha, Krishna Vasanth Valavala
  • Publication number: 20200126888
    Abstract: An integrated circuit (IC) package comprising an IC die, the IC die having a first surface and an opposing second surface. The IC die comprises a semiconductor material. The first surface comprises an active layer. A thermoelectric cooler (TEC) comprising a thermoelectric material is embedded within the IC die between the first surface and the second surface and adjacent to the active layer. The TEC has an annular shape that is substantially parallel to the first and second surfaces of the IC die. The thermoelectric material is confined between an outer sidewall along an outer perimeter of the TEC and an inner sidewall along an inner perimeter of the TEC. The outer and inner sidewalls are substantially orthogonal to the first and second surfaces of the IC die.
    Type: Application
    Filed: October 23, 2018
    Publication date: April 23, 2020
    Applicant: Intel Corporation
    Inventors: Kelly Lofgreen, Chandra Mohan Jha, Krishna Vasanth Valavala
  • Publication number: 20200105639
    Abstract: Embodiments include a microelectronic device package structure having a first die on the substrate. One or more additional dice are on the first die, and a thermal electric cooler (TEC) is on the first die adjacent at least one of the one or more additional dice. A dummy die is on the TEC, wherein the dummy die is thermally coupled to the first die.
    Type: Application
    Filed: October 2, 2018
    Publication date: April 2, 2020
    Applicant: Intel Corporation
    Inventors: Krishna Vasanth Valavala, Ravindranath Mahajan, Chandra Mohan Jha, Kelly Lofgreen, Weihua Tang