Patents by Inventor Krishnashree Achuthan

Krishnashree Achuthan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10295404
    Abstract: A solar monitoring system for measuring solar radiation intensity comprising a tracking unit having two-axis movement comprising, an image capturing head mounted with first and second irradiation measuring units, and a controller. The first irradiation measuring unit comprises a direct normal irradiance (DNI) sensor and the second irradiation measuring unit includes a diffuse horizontal irradiance (DHI) sensor and a global horizontal irradiance (GHI) sensor. The controller receives inputs from the sensors or a software program configured to control orientation of the image capturing head so that the DNI sensor is always exposed to the sun, and the shading disc is always directly between the DHI sensor and the sun.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: May 21, 2019
    Assignee: AMRITA VISHWA VIDYAPEETHAM
    Inventors: Joshua David Freeman, Rahul Kumar, Krishnashree Achuthan
  • Patent number: 10057382
    Abstract: A gateway device has a CPU, a power source, a digital memory, physical communication ports and wireless communication circuitry receiving data from data-gathering devices, an interface to a wide-area network, dedicated hardware pipelines managing the data received, and coded instructions executing on the CPU from a non-transitory medium. The CPU connects physically or wirelessly to one of the data-gathering devices, obtains characterization information for a protocol generic to the data-gathering device, selects code stored in the digital memory, and programs firmware in a dedicated pipeline to receive data from the data-gathering device in the generic protocol.
    Type: Grant
    Filed: January 8, 2016
    Date of Patent: August 21, 2018
    Assignee: Amrita Vishwa Vidyapeetham
    Inventors: Shiju Sathyadevan, Bipin Kunjumon, Harikrishnan Padmanabha Pillai, Krishnashree Achuthan
  • Patent number: 10055607
    Abstract: A system for protecting data managed in a cloud-computing network from malicious data operations includes an Internet-connected server and software executing on the server from a non-transitory physical medium, the software providing a first function for generating one or more security tokens that validate one or more computing operations to be performed on the data, a second function for generating a hash for each token generated, the hash detailing, in a secure fashion, the operation type or types permitted by the one or more tokens, a third function for brokering two-party signature of the one or more tokens, and a fourth function for dynamically activating the one or more signed tokens for a specific time window required to perform the operations permitted by the token.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: August 21, 2018
    Assignee: Amrita Vistiwa Vidyapeetham
    Inventors: Shiju Sathyadevan, P. Venkat Rangan, Krishnashree Achuthan
  • Publication number: 20170316223
    Abstract: A system for protecting data managed in a cloud-computing network from malicious data operations includes an Internet-connected server and software executing on the server from a non-transitory physical medium, the software providing a first function for generating one or more security tokens that validate one or more computing operations to be performed on the data, a second function for generating a hash for each token generated, the hash detailing, in a secure fashion, the operation type or types permitted by the one or more tokens, a third function for brokering two-party signature of the one or more tokens, and a fourth function for dynamically activating the one or more signed tokens for a specific time window required to perform the operations permitted by the token.
    Type: Application
    Filed: July 18, 2017
    Publication date: November 2, 2017
    Applicant: Amrita Vishwa Vidyapeetham
    Inventors: Shiju Sathyadevan, P. Venkat Rangan, Krishnashree Achuthan
  • Patent number: 9710664
    Abstract: A system for protecting data managed in a cloud-computing network from malicious data operations includes an Internet-connected server and software executing on the server from a non-transitory physical medium, the software providing a first function for generating one or more security tokens that validate one or more computing operations to be performed on the data, a second function for generating a hash for each token generated, the hash detailing, in a secure fashion, the operation type or types permitted by the one or more tokens, a third function for brokering two-party signature of the one or more tokens, and a fourth function for dynamically activating the one or more signed tokens for a specific time window required to perform the operations permitted by the token.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: July 18, 2017
    Assignee: Amrita Vishwa Vidyapeetham
    Inventors: Shiju Sathyadevan, P. Venkat Rangan, Krishnashree Achuthan
  • Publication number: 20170094033
    Abstract: A gateway device has a CPU, a power source, a digital memory, physical communication ports and wireless communication circuitry receiving data from data-gathering devices, an interface to a wide-area network, dedicated hardware pipelines managing the data received, and coded instructions executing on the CPU from a non-transitory medium. The CPU connects physically or wirelessly to one of the data-gathering devices, obtains characterization information for a protocol generic to the data-gathering device, selects code stored in the digital memory, and programs firmware in a dedicated pipeline to receive data from the data-gathering device in the generic protocol.
    Type: Application
    Filed: January 8, 2016
    Publication date: March 30, 2017
    Applicant: Amrita Vishwa Vidyapeetham
    Inventors: Shiju Sathyadevan, Bipin Kunjumon, Harikrishnan Padmanabha Pillai, Krishnashree Achuthan
  • Publication number: 20140075568
    Abstract: A system for protecting data managed in a cloud-computing network from malicious data operations includes an Internet-connected server and software executing on the server from a non-transitory physical medium, the software providing a first function for generating one or more security tokens that validate one or more computing operations to be performed on the data, a second function for generating a hash for each token generated, the hash detailing, in a secure fashion, the operation type or types permitted by the one or more tokens, a third function for brokering two-party signature of the one or more tokens, and a fourth function for dynamically activating the one or more signed tokens for a specific time window required to perform the operations permitted by the token.
    Type: Application
    Filed: September 7, 2012
    Publication date: March 13, 2014
    Inventors: Shiju Sathyadevan, P. Venkat Rangan, Krishnashree Achuthan
  • Patent number: 7449413
    Abstract: According to one exemplary embodiment, a method includes a step of forming a polysilicon layer over a substrate by using a deposition process, where the deposition process causes polysilicon nodule defects to form on a top surface of the polysilicon layer. The method further includes performing a polysilicon CMP process on the polysilicon layer, where the polysilicon CMP process removes a substantial percentage of the polysilicon nodule defects from the top surface of the polysilicon layer. The CMP process removes at least 95.0 percent of the polysilicon nodule defects from the top surface of the polysilicon layer. According to this embodiment, the polysilicon CMP process utilizes a polishing pressure that is less than 1.5 psi. The polysilicon CMP process also utilizes a table speed of between 20.0 rpm and 40.0 rpm. The polysilicon CMP process further utilizes a colloidal silica slurry.
    Type: Grant
    Filed: April 11, 2006
    Date of Patent: November 11, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Krishnashree Achuthan, Kashmir Sahota
  • Patent number: 7358191
    Abstract: According to one exemplary embodiment, a method includes a step of forming a number of trenches in a dielectric layer, where the dielectric layer is situated over a wafer. The method further includes forming a metal layer over the dielectric layer and in the trenches such that the metal layer has a dome-shaped profile over the wafer. The method further includes performing a planarizing process to form a number of interconnect lines, where each of the interconnect lines is situated in one of the trenches. The dome-shaped profile of the metal layer causes the interconnect lines to have a reduced thickness variation across the wafer after performing the planarizing process. The interconnect lines are situated in an interconnect metal layer, where the dome-shaped profile of the metal layer causes the interconnect metal layer to have increased sheet resistivity uniformity across the wafer after performing the planarizing process.
    Type: Grant
    Filed: March 24, 2006
    Date of Patent: April 15, 2008
    Assignees: Spansion LLC, Advanced Micro Devices, Inc.
    Inventors: Krishnashree Achuthan, Brad Davis, James Xie, Kashmir Sahota
  • Patent number: 7307002
    Abstract: A method is disclosed for the definition of the poly-1 layer in a semiconductor wafer. A non-critical mask is used to recess field oxides in the periphery prior to poly-1 deposition by an amount equal to the final poly-1 thickness. A complimentary non-critical mask is used to permit CMP of the core to expose the tops of core oxide mesas from the shallow isolation trenches.
    Type: Grant
    Filed: April 4, 2005
    Date of Patent: December 11, 2007
    Assignee: Spansion LLC
    Inventors: Unsoon Kim, Hiroyuki Kinoshita, Yu Sun, Krishnashree Achuthan, Christopher H. Raeder, Christopher M. Foster, Harpreet Kaur Sachar, Kashmir Singh Sahota
  • Patent number: 7294573
    Abstract: According to one exemplary embodiment, a method includes planarizing a layer of polysilicon situated over field oxide regions on a substrate to form polysilicon segments, where the polysilicon segments have top surfaces that are substantially planar with top surfaces of the field oxide regions, and where the field oxide regions have a first height and the polysilicon segments have a first thickness. The method further includes removing a hard mask over a peripheral region of the substrate. According to this exemplary embodiment, the method further includes etching the polysilicon segments to cause the polysilicon segments to have a second thickness, which causes the top surfaces of the polysilicon segments to be situated below the top surfaces of the field oxide regions. The polysilicon segments can be etched by using a wet etch process. The polysilicon segments are situated in a core region of the substrate.
    Type: Grant
    Filed: January 13, 2005
    Date of Patent: November 13, 2007
    Assignees: Spansion LLC, Advanced Micro Devices, Inc.
    Inventors: Krishnashree Achuthan, Unsoon Kim, Kashmir Sahota, Patriz C. Regalado
  • Patent number: 7125776
    Abstract: A method of manufacturing a MOSFET type semiconductor device includes planarizing a gate material layer that is deposited over a channel. The planarization is performed in a multi-step process that includes an initial “rough” planarization and then a “fine” planarization. The slurry used for the finer planarization may include added material that tends to adhere to low areas of the gate material.
    Type: Grant
    Filed: January 7, 2005
    Date of Patent: October 24, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Krishnashree Achuthan, Shibly S. Ahmed, Haihong Wang, Bin Yu
  • Publication number: 20060223278
    Abstract: A method is disclosed for the definition of the poly-1 layer in a semiconductor wafer. A non-critical mask is used to recess field oxides in the periphery prior to poly-1 deposition by an amount equal to the final poly-1 thickness. A complimentary non-critical mask is used to permit CMP of the core to expose the tops of core oxide mesas from the shallow isolation trenches.
    Type: Application
    Filed: April 4, 2005
    Publication date: October 5, 2006
    Inventors: Unsoon Kim, Hiroyuki Kinoshita, Yu Sun, Krishnashree Achuthan, Christopher Raeder, Christopher Foster, Harpreet Sachar, Kashmir Sahota
  • Patent number: 7077728
    Abstract: According to one exemplary embodiment, a method of fabricating an array on a substrate includes forming a layer of a first material adjacent to and over a plurality of segments of a second material on the substrate. The method further includes performing a first CMP process step to form a plurality of segments of the first material, where the plurality of segments of the first material alternate with the plurality of segments of the second material. According to this exemplary embodiment, the method further includes performing a second CMP process step to achieve a target thickness of the plurality of segments of the first material. The first CMP process step comprises a first slurry having particles of a first particle size and the second CMP process step comprises a second slurry having particles of a second particle size, where the second particle size is smaller than the first particle size.
    Type: Grant
    Filed: April 7, 2005
    Date of Patent: July 18, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Krishnashree Achuthan, Kashmir Sahota
  • Patent number: 7052969
    Abstract: A method of manufacturing a planarized semiconductor wafer in which a semiconductor wafer is provided with a chemical-mechanical polishing stop layer deposited thereon. A photoresist layer is processed and used to form a patterned chemical-mechanical polishing stop layer and shallow trenches. A shallow trench isolation material is then grown on the chemical-mechanical polishing stop layer and in the shallow trenches, and is chemical-mechanical polished to the chemical-mechanical polishing stop layer.
    Type: Grant
    Filed: July 3, 2002
    Date of Patent: May 30, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kashmir S. Sahota, Krishnashree Achuthan
  • Patent number: 6989563
    Abstract: A method of protecting a charge trapping dielectric flash memory cell from UV-induced charging, including fabricating a charge trapping dielectric flash memory cell in a semiconductor device; depositing and planarizing an interlevel dielectric layer over the charge trapping dielectric flash memory cell and depositing over the planarized interlevel dielectric layer at least one UV-protective layer, the UV-protective layer including a substantially UV-opaque material.
    Type: Grant
    Filed: February 2, 2004
    Date of Patent: January 24, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Krishnashree Achuthan, Patrick K. Cheung, Cyrus Tabery, Jean Y. Yang, Ning Cheng, Minh Van Ngo
  • Patent number: 6982464
    Abstract: A FinFET-type semiconductor device includes a fin structure on which a relatively thin amorphous silicon layer and then an undoped polysilicon layer is formed. The semiconductor device may be planarized using a chemical mechanical polishing (CMP) in which the amorphous silicon layer acts as a stop layer to prevent damage to the fin structure.
    Type: Grant
    Filed: October 29, 2004
    Date of Patent: January 3, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Krishnashree Achuthan, Shibly S. Ahmed, Haihong Wang, Bin Yu
  • Patent number: 6933219
    Abstract: The invention includes an apparatus and a method of manufacturing such apparatus using a damascene process. The method includes the step of patterning a layer disposed over a substrate to include a line and space pattern. The line and space pattern in the layer includes at least one space comprising a width dimension of a feature to be formed. The feature may be, e.g., a wordline(s)/gate electrode(s). Additionally, the sidewalls of the feature, e.g., the wordline(s)/gate electrode(s) include relatively smooth surfaces.
    Type: Grant
    Filed: November 18, 2003
    Date of Patent: August 23, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Emmanuil H. Lingunis, Krishnashree Achuthan, Minh Van Ngo, Cyrus Tabery, Jean Y. Yang
  • Publication number: 20050118824
    Abstract: A method of manufacturing a MOSFET type semiconductor device includes planarizing a gate material layer that is deposited over a channel. The planarization is performed in a multi-step process that includes an initial “rough” planarization and then a “fine” planarization. The slurry used for the finer planarization may include added material that tends to adhere to low areas of the gate material.
    Type: Application
    Filed: January 7, 2005
    Publication date: June 2, 2005
    Inventors: Krishnashree Achuthan, Shibly Ahmed, Haihong Wang, Bin Yu
  • Publication number: 20050056845
    Abstract: A FinFET-type semiconductor device includes a fin structure on which a relatively thin amorphous silicon layer and then an undoped polysilicon layer is formed. The semiconductor device may be planarized using a chemical mechanical polishing (CMP) in which the amorphous silicon layer acts as a stop layer to prevent damage to the fin structure.
    Type: Application
    Filed: October 29, 2004
    Publication date: March 17, 2005
    Inventors: Krishnashree Achuthan, Shibly Ahmed, Haihong Wang, Bin Yu