Patents by Inventor Krishnashree Achuthan
Krishnashree Achuthan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6855607Abstract: A method of manufacturing a MOSFET type semiconductor device includes planarizing a gate material layer that is deposited over a channel. The planarization is performed in a multi-step process that includes an initial “rough” planarization and then a “fine” planarization. The slurry used for the finer planarization may include added material that tends to adhere to low areas of the gate material.Type: GrantFiled: June 12, 2003Date of Patent: February 15, 2005Assignee: Advanced Micro Devices, Inc.Inventors: Krishnashree Achuthan, Shibly S. Ahmed, Haihong Wang, Bin Yu
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Publication number: 20040253775Abstract: A method of manufacturing a MOSFET type semiconductor device includes planarizing a gate material layer that is deposited over a channel. The planarization is performed in a multi-step process that includes an initial “rough” planarization and then a “fine” planarization. The slurry used for the finer planarization may include added material that tends to adhere to low areas of the gate material.Type: ApplicationFiled: June 12, 2003Publication date: December 16, 2004Inventors: Krishnashree Achuthan, Shibly S. Ahmed, Haihong Wang, Bin Yu
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Patent number: 6812076Abstract: A FinFet-type semiconductor device includes a fin structure on which a relatively thin amorphous silicon layer and then an undoped polysilicon layer is formed. The semiconductor device may be planarized using a chemical mechanical polishing (CMP) in which the amorphous silicon layer acts as a stop layer to prevent damage to the fin structure.Type: GrantFiled: January 8, 2004Date of Patent: November 2, 2004Assignee: Advanced Micro Devices, Inc.Inventors: Krishnashree Achuthan, Shibly S. Ahmed, Haihong Wang, Bin Yu
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Patent number: 6770523Abstract: A method of manufacturing an integrated circuit is provided having a semiconductor wafer. A chemical-mechanical polishing stop layer is deposited on the semiconductor wafer and a first photoresist layer is processed over the chemical-mechanical polishing stop layer. The chemical-mechanical polishing stop layer and the semiconductor wafer are patterned to form a shallow trench and a shallow trench isolation material is deposited on the chemical-mechanical polishing stop layer and in the shallow trench. A second photoresist layer is processed over the shallow trench isolation material leaving the shallow trench uncovered. The uncovered shallow trench is then treated to become a chemical-mechanical polishing stop area. The shallow trench isolation material is then chemical-mechanical polished to be co-planar with the chemical-mechanical stop layer and the chemical-mechanical polishing stop treated area.Type: GrantFiled: July 2, 2002Date of Patent: August 3, 2004Assignee: Advanced Micro Devices, Inc.Inventors: Kashmir S. Sahota, Jeffrey P. Erhardt, Arvind Halliyal, Minh Van Ngo, Krishnashree Achuthan
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Patent number: 6756643Abstract: A FinFET-type semiconductor device includes a fin structure on which a relatively thin amorphous silicon layer and then an undoped polysilicon layer is formed. The semiconductor device may be planarized using a chemical mechanical polishing (CMP) in which the amorphous silicon layer acts as a stop layer to prevent damage to the fin structure.Type: GrantFiled: June 12, 2003Date of Patent: June 29, 2004Assignee: Advanced Micro Devices, Inc.Inventors: Krishnashree Achuthan, Shibly S. Ahmed, Haihong Wang, Bin Yu
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Patent number: 6649511Abstract: A manufacturing method provides a semiconductor substrate with a semiconductor device. A dielectric layer is formed on the semiconductor substrate and an opening provided therein. An barrier layer lines the opening and a seed layer is deposited to line the barrier layer. A conductor core fills the opening over the barrier layer to form a conductor channel. The seed layer is annealed to form an annealed region, which securely bonds the seed layer to the barrier layer and prevents electromigration along the surface between the seed and barrier layers.Type: GrantFiled: October 16, 2002Date of Patent: November 18, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Krishnashree Achuthan, Amit P. Marathe
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Patent number: 6613646Abstract: Shallow trench isolation techniques are disclosed in which a thin nitride layer is formed on a semiconductor substrate, and a trench is formed through the nitride layer and into the semiconductor substrate, which is then filled. The wafer is then planarized using a fixed-abrasive CMP process to mitigate or avoid step height in the shallow trench isolation process. The nitride layer is then removed following planarization.Type: GrantFiled: March 25, 2002Date of Patent: September 2, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Kashmir Sahota, Krishnashree Achuthan
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Patent number: 6610577Abstract: A method for removing polysilicon from isolation regions on a substrate during semiconductor fabrication is disclosed. The method includes depositing a layer of polysilicon over the substrate, and depositing at least one dielectric layer over the polysilicon. The method further includes polishing the polysilicon from the isolation regions, wherein the dielectric layers act as a polishing stop, resulting in regions of polysilicon that are self-aligned to the trench isolation regions.Type: GrantFiled: May 15, 2002Date of Patent: August 26, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Jack F. Thomas, Unsoon Kim, Krishnashree Achuthan
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Patent number: 6607925Abstract: A method for repairing an isolation dielectric damaged during a semiconductor fabrication process is disclosed in which a hard mask material is used to pattern a first material, the first material having openings therein exposing isolation regions comprising a first isolation dielectric layer. The method includes etching the hard mask material from the first material, wherein the etch creates gouges in the first isolation dielectric layer, and depositing a second layer of isolation dielectric over the first material, wherein the second isolation dielectric layer fills the gouges in the first isolation dielectric layer. The method further includes polishing on the second layer of isolation dielectric to remove the second layer of isolation dielectric from the first material.Type: GrantFiled: June 6, 2002Date of Patent: August 19, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Unsoon Kim, Dawn M. Hopper, Yider Wu, Krishnashree Achuthan
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Patent number: 6605517Abstract: A method for reducing nitride residue from a silicon wafer during semiconductor fabrication. The wafer includes a nitride mask defining active regions and isolation regions wherein the isolation regions are formed by trenches. The method includes providing an optimized oxide deposition process in which a temperature gradient of a CVD chamber is improved by performing the following steps. First, at least one silicon wafer is placed into the chamber on a quartz boat having an increased slot size, preferably at least 6 mm. Second, the quartz boat is centered in approximately a center of the chamber so that the wafer is located in a center section of the chamber to avoid the temperature gradient at the ends of the chamber, such that when oxide gas is injected onto the wafer, an oxide layer having a substantially uniform thickness is formed on the wafer.Type: GrantFiled: May 15, 2002Date of Patent: August 12, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Jayendra D. Bhakta, Krishnashree Achuthan, Angela Hui
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Patent number: 6569747Abstract: Shallow trench isolation techniques are disclosed in which a nitride layer is formed on a semiconductor substrate, and a trench is formed through the nitride layer and into the semiconductor substrate. The nitride layer is removed prior to filling the isolation trench, and the fill material is planarized using a fixed-abrasive CMP process to mitigate or avoid step height in the shallow trench isolation process.Type: GrantFiled: March 25, 2002Date of Patent: May 27, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Krishnashree Achuthan, Kashmir Sahota
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Patent number: 6559546Abstract: For fabricating an interconnect structure formed within an interconnect opening surrounded by dielectric material, a layer of diffusion barrier material is formed on at least one wall of the interconnect opening. An activation layer comprised of palladium is formed on the layer of diffusion barrier material when the interconnect opening is immersed in an activation bath comprised of tin ions and palladium ions. The tin ions have a tin ion concentration in the activation bath that is greater than a palladium ion concentration in the activation bath. A layer of seed material is deposited on the activation layer in an electroless deposition process, and the interconnect opening is filled with a conductive fill material grown from the layer of seed material. A layer of silicon rich material may be formed on the layer of diffusion barrier material before deposition of the activation layer such that the activation layer is formed on the layer of silicon rich material.Type: GrantFiled: August 26, 2002Date of Patent: May 6, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Krishnashree Achuthan, Sergey Lopatin
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Patent number: 6498093Abstract: For filling an interconnect opening of an integrated circuit formed on a semiconductor substrate, an underlying material is formed at any exposed walls of the interconnect opening. A sacrificial layer of protective material is formed on the underlying material at the walls of the interconnect opening. The underlying material and the sacrificial layer of protective material are formed without a vacuum break. The protective material of the sacrificial layer is soluble in an acidic catalytic solution used for depositing a catalytic seed layer. The semiconductor substrate having the interconnect opening is placed within an acidic catalytic solution for depositing a catalytic seed layer. The sacrificial layer of protective material is dissolved away from the underlying material by the acidic catalytic solution such that the underlying material is exposed to the acidic catalytic solution.Type: GrantFiled: January 17, 2002Date of Patent: December 24, 2002Assignee: Advanced Micro Devices, Inc.Inventors: Krishnashree Achuthan, Sergey Lopatin
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Patent number: 6498397Abstract: An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A dielectric layer is on the semiconductor substrate and has an opening provided therein. An barrier layer lines the opening and a seed layer is deposited to line the barrier layer. A conductor core fills the opening over the barrier layer to form a conductor channel. The seed layer is annealed to form an annealed region, which securely bonds the seed layer to the barrier layer and prevents electromigration along the surface between the seed and barrier layers.Type: GrantFiled: May 4, 2001Date of Patent: December 24, 2002Assignee: Advanced Micro Devices, Inc.Inventors: Krishnashree Achuthan, Amit P. Marathe
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Patent number: 6472310Abstract: For fabricating an interconnect structure formed within an interconnect opening surrounded by dielectric material, a layer of diffusion barrier material is formed on at least one wall of the interconnect opening. An activation layer comprised of palladium is formed on the layer of diffusion barrier material when the interconnect opening is immersed in an activation bath comprised of tin ions and palladium ions. The tin ions have a tin ion concentration in the activation bath that is greater than a palladium ion concentration in the activation bath. A layer of seed material is deposited on the activation layer in an electroless deposition process, and the interconnect opening is filled with a conductive fill material grown from the layer of seed material. A layer of silicon rich material may be formed on the layer of diffusion barrier material before deposition of the activation layer such that the activation layer is formed on the layer of silicon rich material.Type: GrantFiled: April 8, 2002Date of Patent: October 29, 2002Assignee: Advanced Micro Devices, Inc.Inventors: Krishnashree Achuthan, Sergey Lopatin
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Patent number: 6462409Abstract: A semiconductor wafer polishing method and apparatus therefor are provided having a system housing and a robotic handling system for moving the semiconductor wafer between a belt module and a rotary module for respective linear and rotary polishing. A buff module and a cleaning module are provided in the system housing for buffing and cleaning the semiconductor wafer.Type: GrantFiled: June 6, 2001Date of Patent: October 8, 2002Assignee: Advanced Micro Devices, Inc.Inventors: Krishnashree Achuthan, Christy Mei-Chu Woo
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Patent number: 6426297Abstract: A method is provided for manufacturing an integrated circuit having a semiconductor substrate with a semiconductor device. A dielectric layer is formed on the semiconductor wafer and an opening is formed in the dielectric layer. A barrier layer is deposited to line the opening and a conductor core is deposited to fill the channel opening over the barrier layer. The semiconductor wafer is then subjected to chemical-mechanical polishing using a differential pressure between the center of the semiconductor wafer and its periphery.Type: GrantFiled: July 13, 2001Date of Patent: July 30, 2002Assignee: Advanced Micro Devices, Inc.Inventors: Kashmir S. Sahota, Krishnashree Achuthan, Sergey D. Lopatin
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Patent number: 6423433Abstract: A method of fabricating a semiconductor device having a Cu—Ca—O thin film formed on a Cu surface by immersing the Cu surface into a unique chemical (electroless plating) solution containing salts of calcium (Ca) and copper (Cu), their complexing agents, a reducing agent, a pH adjuster, and surfactants; and a semiconductor device thereby formed for improving Cu interconnect reliability, electromigration resistance, and corrosion resistance. The method controls the parameters of pH, temperature, and time in order to form a uniform conformal Cu-rich Cu—Ca—O thin film, possibly containing carbon (C) and/or sulphur (S), for reducing -electromigration in Cu interconnect lines by decreasing the drift velocity therein which decreases the Cu migration rate in addition to decreasing the void formation rate.Type: GrantFiled: June 29, 2001Date of Patent: July 23, 2002Assignee: Advanced Micro Devices, Inc.Inventors: Sergey Lopatin, Krishnashree Achuthan
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Patent number: 6413869Abstract: A method is provided for manufacturing an integrated circuit having a semiconductor substrate with a semiconductor device. A dielectric layer is formed on the semiconductor substrate and an opening is formed in the dielectric layer. A barrier layer is deposited to line the opening and conductor core is deposited to fill the channel opening over the barrier layer. By using a polishing solution having a dielectric protective characteristic, chemical-mechanical polishing of the conductor core and the barrier layer with the surface of the dielectric layer stops at the surface of the dielectric layer after planarization.Type: GrantFiled: June 8, 2001Date of Patent: July 2, 2002Assignee: Advanced Micro Devices, Inc.Inventors: Krishnashree Achuthan, Steven C. Avanzino, Kashmir S. Sahota
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Patent number: 6291348Abstract: A method of fabricating a semiconductor device having a Cu—Ca—O thin film formed on a Cu surface by immersing the Cu surface into a unique chemical (electroless plating) solution containing salts of calcium (Ca) and copper (Cu), their complexing agents, a reducing agent, a pH adjuster, and surfactants; and a semiconductor device thereby formed for improving Cu interconnect reliability, electromigration resistance, and corrosion resistance. The method controls the parameters of pH, temperature, and time in order to form a uniform conformal Cu-rich Cu—Ca—O thin film, possibly containing carbon (C) and/or sulphur (S), for reducing electromigration in Cu interconnect lines by decreasing the drift velocity therein which decreases the Cu migration rate in addition to decreasing the void formation rate.Type: GrantFiled: November 30, 2000Date of Patent: September 18, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Sergey Lopatin, Krishnashree Achuthan