Patents by Inventor Kristof Kuwawi Darmawikarta

Kristof Kuwawi Darmawikarta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200205279
    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a substrate layer having a surface; a first conductive trace having a first thickness on the surface of the substrate layer; and a second conductive trace having a second thickness on the surface of the substrate layer, wherein the second thickness is different from the first thickness. In some embodiments, the first conductive trace and the second conductive trace have rectangular cross-sections.
    Type: Application
    Filed: December 21, 2018
    Publication date: June 25, 2020
    Applicant: Intel Corporation
    Inventors: Jeremy Ecton, Aleksandar Aleksov, Suddhasattwa Nad, Kristof Kuwawi Darmawikarta, Vahidreza Parichehreh, Veronica Aleman Strong, Xiaoying Guo
  • Publication number: 20200168569
    Abstract: Semiconductor packages having a first layer interconnect portion that includes a coaxial interconnect between a die and a package substrate are described. In an example, the package substrate includes a substrate-side coaxial interconnect electrically connected to a signal line. The die is mounted on the package substrate and includes a die-side coaxial interconnect coupled to the substrate-side coaxial interconnect. The coaxial interconnects can be joined by a solder bond between respective central conductors and shield conductors.
    Type: Application
    Filed: March 30, 2017
    Publication date: May 28, 2020
    Inventors: Sai VADLAMANI, Aleksandar ALEKSOV, Rahul JAIN, Kyu Oh LEE, Kristof Kuwawi DARMAWIKARTA, Robert Alan MAY, Sri Ranga Sai BOYAPATI, Telesphor KAMGAING
  • Publication number: 20200091053
    Abstract: Disclosed herein are integrated circuit (IC) package supports having inductors with magnetic material therein. For example, in some embodiments, an IC package support may include an inductor including a solenoid, a first portion of a magnetic material in an interior of the solenoid, and a second portion of magnetic material outside the interior of the solenoid.
    Type: Application
    Filed: September 14, 2018
    Publication date: March 19, 2020
    Applicant: Intel Corporation
    Inventors: Sameer Paital, Srinivas V. Pietambaram, Yonggang Li, Kristof Kuwawi Darmawikarta, Gang Duan, Krishna Bharath, Michael James Hill
  • Publication number: 20190393172
    Abstract: Semiconductor packages having a die electrically connected to an antenna by a coaxial interconnect are described. In an example, a semiconductor package includes a molded layer between a first antenna patch and a second antenna patch of the antenna. The first patch may be electrically connected to the coaxial interconnect, and the second patch may be mounted on the molded layer. The molded layer may be formed from a molding compound, and may have a stiffness to resist warpage during fabrication and use of the semiconductor package.
    Type: Application
    Filed: March 30, 2017
    Publication date: December 26, 2019
    Inventors: Srinivas V. PIETAMBARAM, Rahul N. MANEPALLI, Kristof Kuwawi DARMAWIKARTA, Robert Alan MAY, Aleksandar ALEKSOV, Telesphor KAMGAING
  • Publication number: 20190393109
    Abstract: Semiconductor packages including package substrates having polymer-derived ceramic cores are described. In an example, a package substrate includes a core layer including a polymer-derived ceramic. The polymer-derived ceramic may include filler particles to control shrinkage and reduce warpage of the core layer during fabrication and use of the package substrate. The core layer may include counterbores or blind holes to embed a contact pad or an electrical interconnect in the core layer. A semiconductor die may be mounted on the package substrate and may be electrically connected to the contact pad or the electrical interconnect.
    Type: Application
    Filed: March 30, 2017
    Publication date: December 26, 2019
    Inventors: Lisa Ying Ying CHEN, Lauren Ashley LINK, Robert Alan MAY, Amruthavalli Pallavi ALUR, Kristof Kuwawi DARMAWIKARTA, Siddharth K. ALUR, Sri Ranga Sai BOYAPATI, Andrew James BROWN, Lilia MAY
  • Publication number: 20190371621
    Abstract: Disclosed herein are integrated circuit (IC) package supports and related apparatuses and methods. For example, in some embodiments, an IC package support may include a non-photoimageable dielectric, and a conductive via through the non-photoimageable dielectric, wherein the conductive via has a diameter that is less than 20 microns. Other embodiments are also disclosed.
    Type: Application
    Filed: June 5, 2018
    Publication date: December 5, 2019
    Applicant: Intel Corporation
    Inventors: Kristof Kuwawi Darmawikarta, Robert May, Sri Ranga Sai Boyapati, Srinivas V. Pietambaram, Chung Kwang Christopher Tan, Aleksandar Aleksov
  • Publication number: 20190363063
    Abstract: Integrated circuit package substrates with high-density interconnect architecture for scaling high-density routing, as well as related structures, devices, and methods, are generally presented. More specifically, integrated circuit package substrates with fan out routing based on a high-density interconnect layer that may include pillars and vias, and integrated cavities for die attachment are presented. Additionally, integrated circuit package substrates with self-aligned pillars and vias formed on the high-density interconnect layer as well as related methods are presented.
    Type: Application
    Filed: December 30, 2016
    Publication date: November 28, 2019
    Applicant: Intel Corporation
    Inventors: Robert Alan MAY, Sri Ranga Sai Boyapati, Kristof Kuwawi Darmawikarta, Srinivas V. Pietambaram, Javier Soto Gonzalez, Kwangmo Chris Lim, Aleksandar Aleksov
  • Publication number: 20190304890
    Abstract: Disclosed herein are via-trace structures with improved alignment, and related package substrates, packages, and computing device. For example, in some embodiments, a package substrate may include a conductive trace, and a conductive via in contact with the conductive trace. The alignment offset between the conductive trace and the conductive via may be less than 10 microns, and conductive trace may have a bell-shaped cross-section or the conductive via may have a flared shape.
    Type: Application
    Filed: April 2, 2018
    Publication date: October 3, 2019
    Applicant: Intel Corporation
    Inventors: Jeremy Ecton, Hiroki Tanaka, Kristof Kuwawi Darmawikarta, Oscar Ojeda, Arnab Roy, Nicholas Haehn
  • Publication number: 20190259631
    Abstract: Integrated circuit (IC) package substrates having high density interconnects with a sputter seed layer containing a copper alloy, as well as related structures, devices, and methods, are disclosed herein. For example, in some embodiments, a package substrate may include a first dielectric layer, a sputter seed layer disposed on the first dielectric layer, wherein the seed layer includes a copper alloy, a patterned conductive layer disposed on the seed layer, and a second dielectric layer over the patterned conductive layer.
    Type: Application
    Filed: December 28, 2016
    Publication date: August 22, 2019
    Inventors: Robert Alan MAY, Kristof Kuwawi Darmawikarta, Sri Ranga Sai Boyapati, Sandeep Gaan, Srinivas V. Pietambaram
  • Publication number: 20190157210
    Abstract: Disclosed herein are package substrates with integrated components, as well as related apparatuses and methods. For example, in some embodiments, an integrated circuit (IC) package, may include: a substrate having opposing first and second faces, an insulating material disposed between the first and second faces, and a thin film transistor (TFT) disposed between the first and second faces, wherein a conductive portion of the TFT is disposed on a layer of the insulating material, and the conductive portion of the TFT is a gate, source, or drain of the TFT; and a die coupled to the first face of the substrate.
    Type: Application
    Filed: May 25, 2016
    Publication date: May 23, 2019
    Applicant: Intel Corporation
    Inventors: Robert Alan May, Kristof Kuwawi Darmawikarta, Sri Ranga Sai Boyapati
  • Patent number: 10026691
    Abstract: Package substrates including conductive interconnects having noncircular cross-sections, and integrated circuit packages incorporating such package substrates, are described. In an example, a conductive pillar having a noncircular pillar cross-section is electrically connected to an escape line routing layer. The escape line routing layer may include several series of conductive pads having noncircular pad cross-sections. Accordingly, conductive traces, e.g., strip line escapes and microstrip escapes, may be routed between the series of conductive pads in a single escape line routing layer.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: July 17, 2018
    Assignee: Intel Corporation
    Inventors: Kristof Kuwawi Darmawikarta, Kyu Oh Lee, Daniel Nicholas Sobieski
  • Publication number: 20170358528
    Abstract: Package substrates including conductive interconnects having noncircular cross-sections, and integrated circuit packages incorporating such package substrates, are described. In an example, a conductive pillar having a noncircular pillar cross-section is electrically connected to an escape line routing layer. The escape line routing layer may include several series of conductive pads having noncircular pad cross-sections. Accordingly, conductive traces, e.g., strip line escapes and microstrip escapes, may be routed between the series of conductive pads in a single escape line routing layer.
    Type: Application
    Filed: June 13, 2016
    Publication date: December 14, 2017
    Inventors: Kristof Kuwawi Darmawikarta, Kyu Oh Lee, Daniel Nicholas Sobieski