Abstract: Embodiments described herein enable a microelectronic assembly that includes: a first substrate comprising glass and at least one inductor, the first substrate having a first side and an opposing second side; a second substrate coupled to the first side of the first substrate; and a plurality of integrated circuit (IC) dies. A first subset of the plurality of IC dies is directly coupled to the second side of the first substrate, a second subset of the plurality of IC dies is directly coupled to the second substrate adjacent to the first substrate, and a third subset of the plurality of IC dies is embedded in the second substrate between the first substrate and the second subset of the plurality of IC dies.

Abstract: Embodiments of a microelectronic assembly that includes: a package substrate, comprising buildup layers of an organic dielectric material and a plurality of layers of conductive traces in the organic dielectric material, the package substrate having a first surface and a second surface opposite the first surface; and a plurality of integrated circuit (IC) dies coupled to the package substrate on the first side. The plurality of layers of conductive traces comprises a pair of stripline traces or microstrips in one of the layers, the stripline traces or microstrips are surrounded by air gap structures in the organic dielectric material, and the air gap structures are exposed on the first surface.

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a conductive pad having a first surface and an opposing second surface; a conductive via coupled to the first surface of the conductive pad; a microelectronic component having a conductive contact, the conductive contact of the microelectronic component electrically coupled, by an interconnect, to the second surface of the conductive pad, wherein a material of the interconnect includes nickel or tin; and a liner between the interconnect and the second surface of the conductive pad, and wherein a material of the liner includes nickel, palladium, or gold. In some embodiments, a bottom surface of the liner is curved outward towards the conductive pad. In some embodiments, the liner also may be on side surfaces of the interconnect.

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a substrate layer having a surface; a first conductive trace having a first thickness on the surface of the substrate layer; and a second conductive trace having a second thickness on the surface of the substrate layer, wherein the second thickness is different from the first thickness. In some embodiments, the first conductive trace and the second conductive trace have rectangular cross-sections.

Abstract: Embodiments of a microelectronic assembly comprise: a package substrate including a first integrated circuit (IC) die embedded therein; and a second IC die coupled to the package substrate and conductively coupled to the first IC die by vias in the package substrate. The package substrate has a first side and an opposing second side, the second IC die is coupled to the first side of the package substrate, the first IC die is between the first side of the package substrate and the second side of the package substrate, the package substrate comprises a plurality of layers of conductive traces in an organic dielectric material, the first IC die is surrounded by the organic dielectric material of the package substrate, the vias are in the organic dielectric material between the first IC die and the first side of the package substrate, and the first IC die comprises through-substrate vias.

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a conductive pad having a first surface, an opposing second surface, and lateral surfaces extending between the first and second surfaces; a conductive via coupled to the first surface of the conductive pad; a liner on the second surface and on the lateral surfaces of the conductive pad, wherein a material of the liner includes nickel, palladium, or gold; a microelectronic component having a conductive contact; and an interconnect electrically coupling the conductive contact of the microelectronic component and the liner on the second surface of the conductive pad, wherein a material of the interconnect includes nickel or tin.

Abstract: Disclosed herein are integrated circuit (IC) package supports and related apparatuses and methods. For example, in some embodiments, a method for forming an IC package support may include forming a first dielectric material having a surface; forming a first conductive via in the first dielectric material, wherein the first conductive via has tapered sidewalls with an angle that is equal to or less than 80 degrees relative to the surface of the first dielectric material; forming a second dielectric material, having a surface, on the first dielectric material; and forming a second conductive via in the second dielectric material, wherein the second conductive via is electrically coupled to the first conductive via, has tapered sidewalls with an angle that is greater than 80 degrees relative to the surface of the second dielectric material, and a maximum diameter between 2 microns and 20 microns.

Abstract: Embodiments of a microelectronic assembly comprise an interposer comprising a dielectric material and a pad of conductive material having at least one of a ceramic liner and fin structures; at least two integrated circuit (IC) dies coupled to the interposer; and a bridge die in the interposer conductively coupled to the at least two IC dies. The bridge die has a first face and an opposing second face, the first face of the bridge die is proximate to the at least two IC dies, and the second face of the bridge die is in contact with the pad.

Abstract: Embodiments of a microelectronic assembly comprise: a package substrate having a first face and an opposing second face, the package substrate comprising a conductive trace in a dielectric material, a conductive structure at least partially surrounding the conductive trace and separated from the conductive trace by the dielectric material; and an integrated circuit (IC) die attached to the first face of the package substrate and coupled to the conductive trace by a conductive pathway through the package substrate. The conductive trace has a non-rectangular cross-section with rounded corners, the conductive structure comprises a plurality of conductive planes parallel to the conductive trace and coupled to a ground connection.

Abstract: Disclosed herein are silver-coated conductive structures in integrated circuit (IC) package supports, as well as related methods and devices. For example, in some embodiments, an IC package support may include a conductive line, a first material layer on a top surface and on side surfaces of the conductive line, the first material layer including silver, and a second material layer on the first material layer, the second material layer including silicon or aluminum, and one or more of nitrogen and oxygen.

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first layer of a substrate having a cavity; a first die at least partially nested in the cavity in the first layer of the substrate, the first die having a surface with conductive contacts; a liner layer on the first layer, in a portion of the cavity, and on and around the first die, wherein a material of the liner layer includes: silicon or aluminum, and one or more of nitrogen, oxygen, and carbon; a second layer on the liner layer, wherein the second layer extends into the cavity and is on and around the first die; and a second die on the second layer, wherein the second die is electrically coupled to the conductive contacts on the first die by conductive vias through the second layer and the liner layer.

Abstract: Embodiments of a microelectronic assembly comprise: a package substrate comprising a conductive trace in a dielectric material, the conductive trace surrounded by a conductive structure coupled to a ground connection, the package substrate further comprising metallization layers alternating with dielectric layers of the dielectric material; and an integrated circuit (IC) die coupled to a surface of the package substrate, the IC die being coupled to the conductive trace by a conductive pathway. The dielectric layers and the metallization layers are parallel to the surface of the package substrate, the conductive trace comprises a trench via in one of the dielectric layers, and the conductive structure comprises grounded plates extending across a length and width of the package substrate in metallization layers on either side of the dielectric layer.

Abstract: Embodiments of a microelectronic assembly comprise a microelectronic assembly, comprising: a package substrate; an interposer coupled to the package substrate, the interposer comprising a dielectric material, a conductive pillar) through the dielectric material and a conductive structure at least partially surrounding the conductive pillar, the conductive structure separated from the conductive pillar by the dielectric material; and an integrated circuit (IC) die coupled to the interposer on a side opposite to the package substrate. The conductive pillar conductively couples the IC die to the package substrate, and the conductive structure is coupled to a ground connection.

Abstract: Disclosed herein are integrated circuit (IC) package supports and related apparatuses and methods. For example, in some embodiments, an IC package support may include a non-photoimageable dielectric, and a conductive via through the non-photoimageable dielectric, wherein the conductive via has a diameter that is less than 20 microns. Other embodiments are also disclosed.

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface with first conductive contacts and an opposing second surface with second conductive contacts, in a first layer; a first material layer on the first surface of the first die, the first material layer including silicon and nitrogen; a second material layer on the first material layer, the second material layer including a photoimageable dielectric; conductive vias through the first and second material layers, wherein respective ones of the conductive vias are electrically coupled to respective ones of the second conductive contacts on the first die; and a second die in a second layer, wherein the second layer on the first layer, and wherein the second die is electrically coupled to the second conductive contacts on the first die by the conductive vias.

Abstract: Microelectronic assemblies including photonic integrated circuits (PICs), related devices and methods, are disclosed herein. For example, in some embodiments, a photonic assembly may include an integrated circuit (IC) in a first layer, wherein the first layer includes a substrate having a first surface, an opposing second surface, and a lateral surface substantially perpendicular to the first and second surfaces, wherein the substrate includes a waveguide between the first and second surfaces, and wherein and the IC is nested in a cavity in the substrate; a PIC in a second layer, wherein the second layer is on the first layer and an active surface of the PIC faces the first layer, and wherein the IC is electrically coupled to the active side of the PIC; and an optical component optically coupled to the active surface of the PIC and the waveguide in the substrate at the second surface.

Abstract: Disclosed herein are via-trace structures with improved alignment, and related package substrates, packages, and computing device. For example, in some embodiments, a package substrate may include a conductive trace, and a conductive via in contact with the conductive trace. The alignment offset between the conductive trace and the conductive via may be less than 10 microns, and conductive trace may have a bell-shaped cross-section or the conductive via may have a flared shape.

Abstract: A microelectronic assembly is disclosed, comprising: a substrate having a core made of glass; and a first integrated circuit (IC) die and a second IC die coupled to a first side of the substrate. The core comprises a cavity, a third IC die is located within the cavity, and the core further comprises one or more conductive through-glass via (TGV) that facilitates electrical coupling between the first side of the substrate and an opposing second side of the substrate. In some embodiments, the cavity is a blind cavity; in other embodiments, the cavity is a through-hole. In some embodiments, the third IC die merely provides lateral coupling between the first IC die and the second IC die; in other embodiments, the third IC die also provides electrical coupling between the first side and the second side of the substrate with through-silicon vias.

Abstract: Integrated circuit package substrates with high-density interconnect architecture for scaling high-density routing, as well as related structures, devices, and methods, are generally presented. More specifically, integrated circuit package substrates with fan out routing based on a high-density interconnect layer that may include pillars and vias, and integrated cavities for die attachment are presented. Additionally, integrated circuit package substrates with self-aligned pillars and vias formed on the high-density interconnect layer as well as related methods are presented.

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a die in a first dielectric layer; and a capacitor including a first conductive pillar and a second conductive pillar in the first dielectric layer, each pillar having a first end and an opposing second end, where the first and second conductive pillars form a first plate of the capacitor; a second dielectric layer on the die and on the second end of the first and second conductive pillars extending at least partially along a first thickness of the first and second conductive pillars and tapering from the second end towards the first end; and a metal layer on the second dielectric layer, wherein the metal layer extends at least partially along a second thickness of the first and second conductive pillars, where the metal layer forms a second plate of the capacitor.