Patents by Inventor Ku-Feng Lin
Ku-Feng Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9673799Abstract: A sensing circuit having a reduced bias clamp and method of operating the sensing circuit are provided. The sensing circuit may include a reference path and a sensing path. The sensing path may include a first transistor, clamping capacitor and a pair of switches. The reference path may include a second transistor, clamping capacitor and another pair of switches. A common gain stage receiving a bias voltage charges the clamping capacitors for the respective paths in a charging mode. The clamping capacitors may be charged in a serial or partially parallel manner during the charging mode. Each path may be coupled to a comparator, which may sense current or voltage changes between the paths during a sense mode. The sensing circuit may be configured to provide for sensing current or voltage changes between multiple sensing and/or reference paths in a parallel or serial manner.Type: GrantFiled: November 16, 2015Date of Patent: June 6, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ku-Feng Lin, Hung-Chang Yu
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Publication number: 20160268344Abstract: The present disclosure provides a method of fabricating a resistive memory array. In one embodiment, a method of fabricating a resistive memory array includes forming a plurality of insulators and a conductive structure on a first substrate, performing a resistor-forming process to transform the insulators into a plurality of resistors, polishing the conductive structure to expose a plurality of contact points respectively electrically connected to the resistors, providing a second substrate having a plurality of transistors and a plurality of interconnect pads, bonding respectively the interconnect pads and the contact points, and removing the first substrate from the resistors and the conductive structure.Type: ApplicationFiled: May 26, 2016Publication date: September 15, 2016Inventors: Ku-Feng LIN, Hung-Chang YU, Kai-Chun LIN, Yu-Der CHIH
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Patent number: 9368552Abstract: A method of fabricating a resistive memory array includes forming a plurality of insulators and a conductive structure on a first substrate, performing a resistor-forming process to transform the insulators into a plurality of resistors, polishing the conductive structure to expose a plurality of contact points respectively electrically connected to the resistors, providing a second substrate having a plurality of transistors and a plurality of interconnect pads, bonding respectively the interconnect pads and the contact points, and removing the first substrate from the resistors and the conductive structure.Type: GrantFiled: November 22, 2013Date of Patent: June 14, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ku-Feng Lin, Hung-Chang Yu, Kai-Chun Lin, Yue-Der Chih
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Patent number: 9330746Abstract: A circuit that includes a current source module, a current sink module and a memory bank is disclosed. Each of the current source module, the current sink module and the memory bank is connected to the first bit/source line and the second bit/source line. The memory bank is bounded by the current source module and the current sink module. When the current source module and the current sink module receive a triggering pulse from the first bit/source line and a select signal with a first state, the current source module is activated to generate an operating current to the first bit/source line that transmits through a conducted memory cell of the memory bank and the current sink module is activated to drain the operating current from the second bit/source line.Type: GrantFiled: March 19, 2014Date of Patent: May 3, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kai-Chun Lin, Hung-Chang Yu, Ku-Feng Lin, Yue-Der Chih
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Publication number: 20160072494Abstract: A sensing circuit having a reduced bias clamp and method of operating the sensing circuit are provided. The sensing circuit may include a reference path and a sensing path. The sensing path may include a first transistor, clamping capacitor and a pair of switches. The reference path may include a second transistor, clamping capacitor and another pair of switches. A common gain stage receiving a bias voltage charges the clamping capacitors for the respective paths in a charging mode. The clamping capacitors may be charged in a serial or partially parallel manner during the charging mode. Each path may be coupled to a comparator, which may sense current or voltage changes between the paths during a sense mode. The sensing circuit may be configured to provide for sensing current or voltage changes between multiple sensing and/or reference paths in a parallel or serial manner.Type: ApplicationFiled: November 16, 2015Publication date: March 10, 2016Inventors: Ku-Feng Lin, Hung-Chang Yu
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Patent number: 9214931Abstract: A sensing circuit having a reduced bias clamp and method of operating the sensing circuit are provided. The sensing circuit may include a reference path and a sensing path. The sensing path may include a first transistor, clamping capacitor and a pair of switches. The reference path may include a second transistor, clamping capacitor and another pair of switches. A common gain stage receiving a bias voltage charges the clamping capacitors for the respective paths in a charging mode. The clamping capacitors may be charged in a serial or partially parallel manner during the charging mode. Each path may be coupled to a comparator, which may sense current or voltage changes between the paths during a sense mode. The sensing circuit may be configured to provide for sensing current or voltage changes between multiple sensing and/or reference paths in a parallel or serial manner.Type: GrantFiled: May 31, 2013Date of Patent: December 15, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ku-Feng Lin, Hung-Chang Yu
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Patent number: 9177621Abstract: A device includes a first switch configured to control a connection between a first voltage node and a capacitor, and a second switch configured to control a connection between a common charge node and the capacitor. The device further includes a plurality of bit-lines, and a plurality of bit-line charge switches, each configured to control a connection between a respective one of the plurality of bit-lines and the common charge node.Type: GrantFiled: August 31, 2012Date of Patent: November 3, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Chang Yu, Ku-Feng Lin
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Patent number: 9165613Abstract: A device includes an amplifier and a first switched current sampler. The first switched current sampler includes a first transistor, a first capacitor, and first, second, and third switches. The first capacitor has a first terminal electrically connected to a gate electrode of the first transistor, and a second terminal electrically connected to a source electrode of the first transistor. The first switch has a first terminal electrically connected to a first current source, and a second terminal electrically connected to the gate electrode of the first transistor. The second switch has a first terminal electrically connected to the first current source, and a second terminal electrically connected to a drain electrode of the first transistor. The third switch has a first terminal electrically connected to the drain electrode of the first transistor, and a second terminal electrically connected to a first input terminal of the amplifier.Type: GrantFiled: September 3, 2013Date of Patent: October 20, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ku-Feng Lin, Hung-Chang Yu, Yue-Der Chih
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Publication number: 20150294696Abstract: A stabilizing circuit is provided that is connected to a biased voltage. The stabilizing circuit is configured to inhibit a change in voltage of the biased voltage caused by a first change in voltage of one or more nodes that are connected to the biased voltage through a first parasitic capacitance. In some embodiments, the stabilizing circuit induces a voltage on the biased voltage through a second parasitic capacitance that changes from a first voltage level to a second voltage level during the first change in voltage such that a total change in parasitic voltage that is induced at the biased voltage during the first change in voltage is close to 0 V.Type: ApplicationFiled: April 10, 2014Publication date: October 15, 2015Inventors: Kai-Chun Lin, Hung-Chang Yu, Ku-Feng Lin, Yue-Der Chih
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Publication number: 20150269997Abstract: A circuit that includes a current source module, a current sink module and a memory bank is disclosed. Each of the current source module, the current sink module and the memory bank is connected to the first bit/source line and the second bit/source line. The memory bank is bounded by the current source module and the current sink module. When the current source module and the current sink module receive a triggering pulse from the first bit/source line and a select signal with a first state, the current source module is activated to generate an operating current to the first bit/source line that transmits through a conducted memory cell of the memory bank and the current sink module is activated to drain the operating current from the second bit/source line.Type: ApplicationFiled: March 19, 2014Publication date: September 24, 2015Applicant: Taiwan Semiconductor Manufacturing CO., LTD.Inventors: Kai-Chun Lin, Hung-Chang Yu, Ku-Feng Lin, Yue-Der Chih
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Publication number: 20150234403Abstract: A low-dropout (LDO) regulator is provided. The LDO regulator comprises a first circuit operating as a closed loop control system. The first circuit is configured to control a voltage at a first node such that the voltage at the first node is substantially equal to a specified regulator output voltage. The LDO regulator comprises a second circuit operating as an open loop control system. The second circuit is configured to increase the voltage at the first node when a current flowing through a load changes from a first current to a second current. The first current is substantially equal to 0 amperes.Type: ApplicationFiled: February 17, 2014Publication date: August 20, 2015Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: Yuan-Long Siao, Ku-Feng Lin, Kai-Chun Lin, Hung-Chang Yu, Chia-Fu Lee, Yue-Der Chih
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Publication number: 20150144860Abstract: The present disclosure provides a method of fabricating a resistive memory array. In one embodiment, a method of fabricating a resistive memory array includes forming a plurality of insulators and a conductive structure on a first substrate, performing a resistor-forming process to transform the insulators into a plurality of resistors, polishing the conductive structure to expose a plurality of contact points respectively electrically connected to the resistors, providing a second substrate having a plurality of transistors and a plurality of interconnect pads, bonding respectively the interconnect pads and the contact points, and removing the first substrate from the resistors and the conductive structure.Type: ApplicationFiled: November 22, 2013Publication date: May 28, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ku-Feng LIN, Hung-Chang YU, Kai-Chun LIN, Yue-Der CHIH
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Publication number: 20150063048Abstract: A device includes an amplifier and a first switched current sampler. The first switched current sampler includes a first transistor, a first capacitor, and first, second, and third switches. The first capacitor has a first terminal electrically connected to a gate electrode of the first transistor, and a second terminal electrically connected to a source electrode of the first transistor. The first switch has a first terminal electrically connected to a first current source, and a second terminal electrically connected to the gate electrode of the first transistor. The second switch has a first terminal electrically connected to the first current source, and a second terminal electrically connected to a drain electrode of the first transistor. The third switch has a first terminal electrically connected to the drain electrode of the first transistor, and a second terminal electrically connected to a first input terminal of the amplifier.Type: ApplicationFiled: September 3, 2013Publication date: March 5, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ku-Feng Lin, Hung-Chang Yu, Yue-Der Chih
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Patent number: 8923040Abstract: A memory has magnetic tunnel junction elements with different resistances in different logic states, for bit positions in memory words accessed by a word line signal coupling each bit cell in the addressed word between a bit line and source line for that bit position. The bit lines and source lines are longer and shorter at different word line locations, causing a resistance body effect. A clamping transistor couples the bit line to a sensing circuit when reading, applying a current through the bit cell and producing a read voltage compared by the sensing circuit to a reference such as a comparable voltage from a reference bit cell circuit having a similar structure. A drive control varies an input to the switching transistor as a function of the word line location, e.g., by word line address, to offset the different bit and source line resistances.Type: GrantFiled: January 30, 2013Date of Patent: December 30, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kai-Chun Lin, Hung-Chang Yu, Ku-Feng Lin, Yue-Der Chih
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Patent number: 8908439Abstract: A word line driver circuit includes a first transistor having its gate coupled to a first node configured to receive a word line select signal. A second transistor has its gate coupled to the first node and a drain coupled to a drain of the first transistor at a second node that is coupled to a word line. A word line assist control circuit is coupled to the first node, to the word line, and to a gate of a third transistor. The word line assist control circuit is configured to turn on or turn off the third transistor to adjust a voltage of the word line.Type: GrantFiled: December 6, 2012Date of Patent: December 9, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ku-Feng Lin, Hung-Chang Yu, Kai-Chun Lin
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Patent number: 8842489Abstract: A word line driver of a semiconductor memory includes logic circuitry for coupling a word line to a first node set at a first voltage level when the word line driver is in a first state or to a second node set at a second voltage level when the word line driver is in a second state. A capacitor is configured to be charged to a third voltage level that is greater than the first and second voltage levels. First and second transistors are configured to selectively couple the word line to the capacitor and to a third node set at a fourth voltage level when the word line driver is in a third state. The fourth voltage level is greater than the first voltage level and less than the second voltage level.Type: GrantFiled: April 16, 2012Date of Patent: September 23, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hung-Chang Yu, Ku-Feng Lin, Kai-Chun Lin, Yue-Der Chih
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Publication number: 20140266312Abstract: A sensing circuit having a reduced bias clamp and method of operating the sensing circuit are provided. The sensing circuit may include a reference path and a sensing path. The sensing path may include a first transistor, clamping capacitor and a pair of switches. The reference path may include a second transistor, clamping capacitor and another pair of switches. A common gain stage receiving a bias voltage charges the clamping capacitors for the respective paths in a charging mode. The clamping capacitors may be charged in a serial or partially parallel manner during the charging mode. Each path may be coupled to a comparator, which may sense current or voltage changes between the paths during a sense mode. The sensing circuit may be configured to provide for sensing current or voltage changes between multiple sensing and/or reference paths in a parallel or serial manner.Type: ApplicationFiled: May 31, 2013Publication date: September 18, 2014Inventors: Ku-Feng Lin, Hung-Chang Yu
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Publication number: 20140211549Abstract: A memory has magnetic tunnel junction elements with different resistances in different logic states, for bit positions in memory words accessed by a word line signal coupling each bit cell in the addressed word between a bit line and source line for that bit position. The bit lines and source lines are longer and shorter at different word line locations, causing a resistance body effect. A clamping transistor couples the bit line to a sensing circuit when reading, applying a current through the bit cell and producing a read voltage compared by the sensing circuit to a reference such as a comparable voltage from a reference bit cell circuit having a similar structure. A drive control varies an input to the switching transistor as a function of the word line location, e.g., by word line address, to offset the different bit and source line resistances.Type: ApplicationFiled: January 30, 2013Publication date: July 31, 2014Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kai-Chun LIN, Hung-Chang YU, Ku-Feng LIN, Yue-Der CHIH
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Publication number: 20140071750Abstract: A word line driver circuit includes a first transistor having its gate coupled to a first node configured to receive a word line select signal. A second transistor has its gate coupled to the first node and a drain coupled to a drain of the first transistor at a second node that is coupled to a word line. A word line assist control circuit is coupled to the first node, to the word line, and to a gate of a third transistor. The word line assist control circuit is configured to turn on or turn off the third transistor to adjust a voltage of the word line.Type: ApplicationFiled: December 6, 2012Publication date: March 13, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ku-Feng LIN, Hung-Chang YU, Kai-Chun LIN
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Publication number: 20140064000Abstract: A device includes a first switch configured to control a connection between a first voltage node and a capacitor, and a second switch configured to control a connection between a common charge node and the capacitor. The device further includes a plurality of bit-lines, and a plurality of bit-line charge switches, each configured to control a connection between a respective one of the plurality of bit-lines and the common charge node.Type: ApplicationFiled: August 31, 2012Publication date: March 6, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hung-Chang Yu, Ku-Feng Lin