Patents by Inventor Kuan-Chih Huang

Kuan-Chih Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11955484
    Abstract: A semiconductor device includes a semiconductor substrate having a first region and a second region, insulators, gate stacks, and first and second S/Ds. The first and second regions respectively includes at least one first semiconductor fin and at least one second semiconductor fin. A width of a middle portion of the first semiconductor fin is equal to widths of end portions of the first semiconductor fin. A width of a middle portion of the second semiconductor fin is smaller than widths of end portions of the second semiconductor fin. The insulators are disposed on the semiconductor substrate. The first and second semiconductor fins are sandwiched by the insulators. The gate stacks are over a portion of the first semiconductor fin and a portion of the second semiconductor fin. The first and second S/Ds respectively covers another portion of the first semiconductor fin and another portion of the second semiconductor fin.
    Type: Grant
    Filed: June 10, 2022
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Jung Chen, I-Chih Chen, Chih-Mu Huang, Kai-Di Wu, Ming-Feng Lee, Ting-Chun Kuan
  • Publication number: 20230246396
    Abstract: A connector assembly includes a guiding shield cage, a receptacle connector, a partitioning bracket and a movable heat sink. The receptacle connector is provided to a rear segment of an interior of the guiding shield cage, the receptacle connector has an upper receptacle and a lower receptacle. The partitioning bracket is provided in the guiding shield cage, the partitioning bracket and the guiding shield cage together define an upper receiving space which corresponds to the upper receptacle and a lower receiving space which corresponds to the lower receptacle. The movable heat sink is assembled to the partitioning bracket, the movable heat sink is capable of moving relative to the partitioning bracket between a front position where the movable heat sink is positioned in front of a front end of the upper receptacle a front end of the lower receptacle and a rearward position where the movable heat sink at least partially enters into between the upper receptacle and the lower receptacle.
    Type: Application
    Filed: January 19, 2023
    Publication date: August 3, 2023
    Inventors: Ming-Huei KAO, Kuan-Chih HUANG, Vivek SHAH, Saiyed Muhammad Hasan ALI, Hui-Hsuan YANG, Kuan-Lin PENG, Wei-Cheng LIN
  • Publication number: 20220320827
    Abstract: A photonic crystal surface emitting laser device including at least one photonic crystal surface emitting laser unit is provided. The photonic crystal surface emitting laser unit includes a light-emitting layer, a photonic crystal layer, a doped semiconductor layer, and a diffractive grating. The light-emitting layer is configured to emit a light beam. The photonic crystal layer is disposed on one side of the light-emitting layer. The doped layer is disposed on another side of the light-emitting layer. The diffractive grating is disposed on the photonic crystal layer or the doped semiconductor layer.
    Type: Application
    Filed: March 31, 2022
    Publication date: October 6, 2022
    Applicant: Phosertek Corporation
    Inventors: Lih-Ren Chen, Kuo-Bin Hong, Tien-Chang Lu, Chien-Hung Lin, Hsiu-Ling Chen, Kuan-Chih Huang
  • Patent number: 10510661
    Abstract: Semiconductor devices and methods of forming the same are provided. One of the semiconductor devices comprises a conductive layer, a first dielectric layer disposed over the conductive layer, a magnetic layer disposed over the first dielectric layer, and a plurality of tantalum layers and a plurality of tantalum oxide layers alternately disposed between the magnetic layer and the first dielectric layer.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hon-Lin Huang, Chen-Shien Chen, Chin-Yu Ku, Kuan-Chih Huang, Wei-Li Huang
  • Publication number: 20190096804
    Abstract: Semiconductor devices and methods of forming the same are provided. One of the semiconductor devices comprises a conductive layer, a first dielectric layer disposed over the conductive layer, a magnetic layer disposed over the first dielectric layer, and a plurality of tantalum layers and a plurality of tantalum oxide layers alternately disposed between the magnetic layer and the first dielectric layer.
    Type: Application
    Filed: November 29, 2018
    Publication date: March 28, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hon-Lin Huang, Chen-Shien Chen, Chin-Yu Ku, Kuan-Chih Huang, Wei-Li Huang
  • Patent number: 10170536
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a first passivation layer over the substrate; a second passivation layer over the first passivation layer; a magnetic layer in the second passivation layer; and an etch stop layer between the magnetic layer and the first passivation layer, wherein the etch stop layer includes at least one acid resistant layer, and the acid resistant layer includes a metal oxide. A method for manufacturing a semiconductor structure is also disclosed.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: January 1, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hung-Wen Hsu, Yen-Shuo Su, Jiech-Fun Lu, Kuan Chih Huang, Tze Yun Chou, Chun-Mao Chiu, Tao-Sheng Chang
  • Patent number: 10163781
    Abstract: Semiconductor devices and methods of forming the same are disclosed. One of the semiconductor devices includes a conductive layer, a first dielectric layer, a magnetic layer and an etch stop stack. The first dielectric layer is disposed over the conductive layer. The magnetic layer is disposed over the first dielectric layer. The etch stop stack is disposed between the magnetic layer and the first dielectric layer. The etch stop stack includes a second dielectric layer and a plurality of unit layers between the second dielectric layer and the magnetic layer, and each of the plurality of unit layers comprises a tantalum layer and a tantalum oxide layer on the tantalum layer.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hon-Lin Huang, Chen-Shien Chen, Chin-Yu Ku, Kuan-Chih Huang, Wei-Li Huang
  • Publication number: 20180366536
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a first passivation layer over the substrate; a second passivation layer over the first passivation layer; a magnetic layer in the second passivation layer; and an etch stop layer between the magnetic layer and the first passivation layer, wherein the etch stop layer includes at least one acid resistant layer, and the acid resistant layer includes a metal oxide. A method for manufacturing a semiconductor structure is also disclosed.
    Type: Application
    Filed: June 19, 2017
    Publication date: December 20, 2018
    Inventors: HUNG-WEN HSU, YEN-SHUO SU, JIECH-FUN LU, KUAN CHIH HUANG, TZE YUN CHOU, CHUN-MAO CHIU, TAO-SHENG CHANG
  • Publication number: 20180350739
    Abstract: Semiconductor devices and methods of forming the same are disclosed. One of the semiconductor devices includes a conductive layer, a first dielectric layer, a magnetic layer and an etch stop stack. The first dielectric layer is disposed over the conductive layer. The magnetic layer is disposed over the first dielectric layer. The etch stop stack is disposed between the magnetic layer and the first dielectric layer. The etch stop stack includes a second dielectric layer and a plurality of unit layers between the second dielectric layer and the magnetic layer, and each of the plurality of unit layers comprises a tantalum layer and a tantalum oxide layer on the tantalum layer.
    Type: Application
    Filed: October 31, 2017
    Publication date: December 6, 2018
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hon-Lin Huang, Chen-Shien Chen, Chin-Yu Ku, Kuan-Chih Huang, Wei-Li Huang
  • Patent number: 10037951
    Abstract: A semiconductor package includes a radio frequency (RF) module, an antenna, an electromagnetic (EM) shield and a first mold body. The RF module having a bottom and a lateral side, wherein, the RF module includes a module board at the bottom. The antenna located at the lateral side of the RF module. The EM shield covering the RF module, wherein the EM shield includes a side wall disposed along the lateral side of the RF module, and the side wall of the EM shield is between the RF module and the antenna. The first mold body fixing the EM shield and the antenna, such that the antenna is spaced apart from the side wall of the EM shield by a predetermined distance.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: July 31, 2018
    Assignee: CYNTEC CO., LTD.
    Inventors: Chia-Hsien Shen, Kuan-Chih Huang, Shu-Wei Chang, Joseph D. S. Deng
  • Publication number: 20180151518
    Abstract: A semiconductor package includes a radio frequency (RF) module, an antenna, an electromagnetic (EM) shield and a first mold body. The RF module having a bottom and a lateral side, wherein, the RF module includes a module board at the bottom. The antenna located at the lateral side of the RF module. The EM shield covering the RF module, wherein the EM shield includes a side wall disposed along the lateral side of the RF module, and the side wall of the EM shield is between the RF module and the antenna. The first mold body fixing the EM shield and the antenna, such that the antenna is spaced apart from the side wall of the EM shield by a predetermined distance.
    Type: Application
    Filed: November 29, 2016
    Publication date: May 31, 2018
    Applicant: CYNTEC CO., LTD.
    Inventors: Chia-Hsien SHEN, Kuan-Chih HUANG, Shu-Wei CHANG, Joseph D. S. DENG
  • Patent number: 9691710
    Abstract: A semiconductor package includes a substrate, a plurality of pin pads, a radio frequency (RF) pad, a semiconductor component, at least one surface mount device (SMD) component, a mold compound, a printed circuit board (PCB) antenna and a conductive solder. The RF pad is used to receive or transmit an RF signal on the top side of the substrate. The SMD component is mounted on the RF pad. The mold compound on the top side of the substrate covers the semiconductor component and the SMD component. The PCB antenna is located on the mold compound. Wherein, the conductive solder and the SMD component are stacked between the RF pad and a feeding structure of the PCB antenna.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: June 27, 2017
    Assignee: CYNTEC CO., LTD
    Inventors: Joseph D. S. Deng, Chia-Hsien Shen, Shu-Wei Chang, Kuan-Chih Huang
  • Publication number: 20170162514
    Abstract: A semiconductor package includes a substrate, a plurality of pin pads, a radio frequency (RF) pad, a semiconductor component, at least one surface mount device (SMD) component, a mold compound, a printed circuit board (PCB) antenna and a conductive solder. The RF pad is used to receive or transmit an RF signal on the top side of the substrate. The SMD component is mounted on the RF pad. The mold compound on the top side of the substrate covers the semiconductor component and the SMD component. The PCB antenna is located on the mold compound. Wherein, the conductive solder and the SMD component are stacked between the RF pad and a feeding structure of the PCB antenna.
    Type: Application
    Filed: December 4, 2015
    Publication date: June 8, 2017
    Applicant: CYNTEC CO., LTD.
    Inventors: Joseph D. S. DENG, Chia-Hsien SHEN, Shu-Wei CHANG, Kuan-Chih HUANG
  • Patent number: 9440501
    Abstract: An ID code learning device includes a RF transceiving module, a received signal strength indication (RSSI) module, and a processing circuit. The RF transceiving module receives RF signals, and each of the RF signals contains an ID code. The RSSI module is electrically connected to the RF transceiving module to detect signal strengths of the RF signals received by the RF transceiving module. The processing circuit is electrically connected to the RF transceiving module and the received signal strength indication module respectively. The received signal strength indication module detects the RF signal with the highest signal strength, the processing circuit pairs the ID code thereof with a predetermined tire location code, and then the RF transceiving module transmits a pairing result out.
    Type: Grant
    Filed: August 15, 2014
    Date of Patent: September 13, 2016
    Assignee: MOBILETRON ELECTRONICS CO., LTD.
    Inventors: Shiao-Hwa Huang, Kuan-Chih Huang, Yu-Liang Chou
  • Patent number: 9406833
    Abstract: Neutron-detecting structures and methods of fabrication are provided which include: a substrate with a plurality of cavities extending into the substrate from a surface; a p-n junction within the substrate and extending, at least in part, in spaced opposing relation to inner cavity walls of the substrate defining the plurality of cavities; and a neutron-responsive material disposed within the plurality of cavities. The neutron-responsive material is responsive to neutrons absorbed for releasing ionization radiation products, and the p-n junction within the substrate spaced in opposing relation to and extending, at least in part, along the inner cavity walls of the substrate reduces leakage current of the neutron-detecting structure.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: August 2, 2016
    Assignee: RENSSELAER POLYTECHNIC INSTITUTE
    Inventors: Rajendra P. Dahal, Jacky Kuan-Chih Huang, James J. Q. Lu, Yaron Danon, Ishwara B. Bhat
  • Publication number: 20150380593
    Abstract: Neutron-detecting structures and methods of fabrication are provided which include: a substrate with a plurality of cavities extending into the substrate from a surface; a p-n junction within the substrate and extending, at least in part, in spaced opposing relation to inner cavity walls of the substrate defining the plurality of cavities; and a neutron-responsive material disposed within the plurality of cavities. The neutron-responsive material is responsive to neutrons absorbed for releasing ionization radiation products, and the p-n junction within the substrate spaced in opposing relation to and extending, at least in part, along the inner cavity walls of the substrate reduces leakage current of the neutron-detecting structure.
    Type: Application
    Filed: September 10, 2015
    Publication date: December 31, 2015
    Applicant: RENSSELAER POLYTECHNIC INSTITUTE
    Inventors: Rajendra P. DAHAL, Jacky Kuan-Chih HUANG, James J.Q. LU, Yaron DANON, Ishwara B. BHAT
  • Patent number: 9151853
    Abstract: Neutron-detecting structures and methods of fabrication are provided which include: a substrate with a plurality of cavities extending into the substrate from a surface; a p-n junction within the substrate and extending, at least in part, in spaced opposing relation to inner cavity walls of the substrate defining the plurality of cavities; and a neutron-responsive material disposed within the plurality of cavities. The neutron-responsive material is responsive to neutrons absorbed for releasing ionization radiation products, and the p-n junction within the substrate spaced in opposing relation to and extending, at least in part, along the inner cavity walls of the substrate reduces leakage current of the neutron-detecting structure.
    Type: Grant
    Filed: November 7, 2013
    Date of Patent: October 6, 2015
    Assignee: RENSSELAER POLYTECHNIC INSTITUTE
    Inventors: Rajendra P. Dahal, Jacky Kuan-Chih Huang, James J. Q. Lu, Yaron Danon, Ishwara B. Bhat
  • Publication number: 20150068893
    Abstract: A biosensor test device of this disclosure includes a biosensor test strip and biosensor monitor connecting with the biosensor test strip. The biosensor test strip includes a base layer and at least one test section. The test section includes a first electrode, a second electrode, a first track, a second track, a first contact pad, a second contact pad and a reaction zone formed on a base layer. The first track is electrically connected to both the first electrode and the first contact pad. The second track is electrically connected to both the second electrode and the second contact pad. The reaction zone is coated with reagents which contact at least one of the first electrode or the second electrode.
    Type: Application
    Filed: September 10, 2014
    Publication date: March 12, 2015
    Inventors: JEN-FANG LEE, Kuan-Chih Huang
  • Publication number: 20150068923
    Abstract: The disclosure is directed to biosensor monitors, test strips and activation mechanisms and methods thereof. The biosensor monitor is for verifying a test strip to be used with the biosensor monitor. The monitor includes verification components located within the monitor and accessible to a test strip to be inserted into the biosensor monitor. The verification components interact with verification portions of the test strip to allow the biosensor monitor to verify the test strip before the biosensor monitor tests biological material on the test strip. A test strip and methods are also described.
    Type: Application
    Filed: September 10, 2014
    Publication date: March 12, 2015
    Inventors: JEN-FANG LEE, KUAN-CHIH HUANG
  • Publication number: 20150054640
    Abstract: An ID code learning device includes a RF transceiving module, a received signal strength indication (RSSI) module, and a processing circuit. The RF transceiving module receives RF signals, and each of the RF signals contains an ID code. The RSSI module is electrically connected to the RF transceiving module to detect signal strengths of the RF signals received by the RF transceiving module. The processing circuit is electrically connected to the RF transceiving module and the received signal strength indication module respectively. The received signal strength indication module detects the RF signal with the highest signal strength, the processing circuit pairs the ID code thereof with a predetermined tire location code, and then the RF transceiving module transmits a pairing result out.
    Type: Application
    Filed: August 15, 2014
    Publication date: February 26, 2015
    Inventors: SHIAO-HWA HUANG, KUAN-CHIH HUANG, YU-LIANG CHOU