Patents by Inventor Kuan-Lun Cheng

Kuan-Lun Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200259014
    Abstract: A method includes forming a first semiconductor layer over a substrate. A second semiconductor layer is formed over the first semiconductor layer. The first semiconductor layer and the second semiconductor layer are etched to form a fin structure that extends from the substrate. The fin structure has a remaining portion of first semiconductor layer and a remaining portion of the second semiconductor layer atop the remaining portion of the first semiconductor layer. A capping layer is formed to wrap around three sides of the fin structure. At least a portion of the capping layer and at least a portion of the remaining portion of the second semiconductor layer in the fin structure are oxidized to form an oxide layer wrapping around three sides of the fin structure.
    Type: Application
    Filed: April 27, 2020
    Publication date: August 13, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng CHING, Kuan-Ting PAN, Kuan-Lun CHENG, Chih-Hao WANG
  • Patent number: 10741672
    Abstract: A method of forming a fin field effect transistors (finFET) on a substrate includes forming a fin structure on the substrate, forming a protective layer on the fin structure, and forming a polysilicon structure on the protective layer. The method further includes modifying the polysilicon structure such that a first horizontal dimension of a first portion of the modified polysilicon structure is smaller than a second horizontal dimension of a second portion of the modified polysilicon structure. The method further includes replacing the modified polysilicon structure with a gate structure having a first horizontal dimension of a first portion of the gate structure that is smaller than a second horizontal dimension of a second portion of the gate structure.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: August 11, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.
    Inventors: Kuo-Cheng Ching, Chih-Hao Wang, Ching-Wei Tsai, Kuan-Lun Cheng
  • Patent number: 10720503
    Abstract: A semiconductor device includes a semiconductor substrate, a first fin structure and a second fin structure. The first fin structure includes a first fin and at least two first nano wires disposed above the first fin, and the first fin protrudes from the semiconductor substrate. The second fin structure includes a second fin and at least two second nano wires disposed above the second fin, and the second fin protrudes from the semiconductor substrate. Each first nano wire has a first width different from a second width of each second nano wire.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: July 21, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Ching, Shi-Ning Ju, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 10714394
    Abstract: A method of forming a fin field effect transistor (finFET) on a substrate includes forming a fin structure on the substrate and forming a shallow trench isolation (STI) region on the substrate. First and second fin portions of the fin structure extend above a top surface of the STI region. The method further includes oxidizing the first fin portion to convert a first material of the first fin portion to a second material. The second material is different from the first material of the first fin portion and a material of the second fin portion. The method further includes forming an oxide layer on the oxidized first fin portion and the second fin portion and forming first and second polysilicon structures on the oxide layer.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: July 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Cheng Ching, Chih-Hao Wang, Kuan-Lun Cheng, Yen-Ming Chen
  • Publication number: 20200176590
    Abstract: Present disclosure provides a semiconductor structure, including a semiconductor substrate, an insulator fin over the semiconductor substrate, the insulator fin having a principle dimension, from a cross sectional perspective, perpendicular to a top surface of the semiconductor substrate, and a semiconductor capping layer cover the insulator fin along the principle dimension. A method for manufacturing a semiconductor structure is also disclosed in the present disclosure.
    Type: Application
    Filed: June 19, 2019
    Publication date: June 4, 2020
    Inventors: CHI-YI CHUANG, CHING-WEI TSAI, KUAN-LUN CHENG, CHIH-HAO WANG
  • Publication number: 20200176448
    Abstract: A semiconductor arrangement includes a well region, a transistor over the well region, a conductive line in conductive contact with a first source/drain region of the transistor and having a sidewall in conductive contact with a sidewall of the well region, and a liner layer disposed between the sidewall of the conductive line and the sidewall of the well region. A method includes forming a well region in a semiconductor layer. A first fin and a second fin are formed over the well region. A first spacer is formed on the first fin and a second spacer is formed on the second fin. A portion of the well region positioned between the first spacer and the second spacer is removed to define a trench. A liner layer is formed in the trench, and a conductive line is formed in the trench over the liner layer. The conductive line conductively contacts the well region.
    Type: Application
    Filed: November 26, 2019
    Publication date: June 4, 2020
    Inventors: Yu-Xuan Huang, Ching-Wei Tsai, Kuan-Lun Cheng
  • Publication number: 20200176449
    Abstract: Aspects of the disclosure provide a semiconductor device and a method for forming the semiconductor device. The semiconductor device includes a plurality of nanostructures stacked over a substrate in a vertical direction, a source/drain terminal adjoining the plurality of nanostructures, and a gate structure around the plurality of nanostructures. The gate structure includes a metal cap connecting adjacent two of the plurality of nanostructures and a metal layer partially surrounding the plurality of nanostructures.
    Type: Application
    Filed: February 4, 2020
    Publication date: June 4, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Cheng CHING, Shi Ning JU, Ching-Wei TSAI, Kuan-Lun CHENG, Chih-Hao WANG
  • Publication number: 20200176326
    Abstract: In an embodiment, a method includes: forming a first recess and a second recess in a substrate; growing a first epitaxial material stack in the first recess, the first epitaxial material stack including alternating layers of a first semiconductor material and a second semiconductor material, the layers of the first epitaxial material stack being undoped; growing a second epitaxial material stack in the second recess, the second epitaxial material stack including alternating layers of the first semiconductor material and the second semiconductor material, a first subset of the second epitaxial material stack being undoped, a second subset of the second epitaxial material stack being doped; patterning the first epitaxial material stack and the second epitaxial material stack to respectively form first nanowires and second nanowires; and forming a first gate structure around the first nanowires and a second gate structure around the second nanowires.
    Type: Application
    Filed: July 8, 2019
    Publication date: June 4, 2020
    Inventors: Yi-Bo Liao, Kai-Chieh Yang, Ching-Wei Tsai, Kuan-Lun Cheng
  • Patent number: 10672892
    Abstract: Semiconductor structures including active fin structures, dummy fin structures, epitaxy layers, a Ge containing oxide layer and methods of manufacture thereof are described. By implementing the Ge containing oxide layer on the surface of the epitaxy layers formed on the source/drain regions of some of the FinFET devices, a self-aligned epitaxy process is enabled. By implementing dummy fin structures and a self-aligned etch, both the epitaxy layers and metal gate structures from adjacent FinFET devices are isolated in a self-aligned manner.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: June 2, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Cheng Ching, Chih-Hao Wang, Kuan-Lun Cheng
  • Patent number: 10658490
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes active gate stacks over the fin structure. The semiconductor device structure further includes a dummy gate stack over the fin structure. The dummy gate stack is between the active gate stacks. In addition, the semiconductor device structure includes spacer elements over sidewalls of the dummy gate stack and the active gate stacks. The semiconductor device structure also includes an isolation feature below the dummy gate stack, the active gate stacks and the spacer elements. The isolation feature extends into the fin structure from the bottom of the dummy gate stack such that the isolation feature is surrounded by the fin structure.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: May 19, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Ching, Shi-Ning Ju, Kuan-Ting Pan, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 10658370
    Abstract: A semiconductor device includes a substrate having a semiconductor fin, in which the semiconductor fin has a first sidewall and a second sidewall opposite to the first sidewall; an epitaxy structure in contact with the first sidewall of the semiconductor fin; and a spacer in contact with the second sidewall of the semiconductor fin and the epitaxy structure.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: May 19, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tetsu Ohtou, Ching-Wei Tsai, Kuan-Lun Cheng, Yasutoshi Okuno, Jiun-Jia Huang
  • Patent number: 10658362
    Abstract: A FinFET device includes a fin, an epitaxial layer disposed at a side surface of the fin, a contact disposed on the epitaxial layer and on the fin. The contact includes an epitaxial contact portion and a metal contact portion disposed on the epitaxial contact portion. The doping concentration of the epitaxial contact portion is higher than a doping concentration of the epitaxial layer.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: May 19, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Ching, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
  • Publication number: 20200152632
    Abstract: A method includes etching a hybrid substrate to form a recess extending into the hybrid substrate. The hybrid substrate includes a first semiconductor layer having a first surface orientation, a dielectric layer over the first semiconductor layer, and a second semiconductor layer having a second surface orientation different from the first surface orientation. After the etching, a top surface of the first semiconductor layer is exposed to the recess. A spacer is formed on a sidewall of the recess. The spacer contacts a sidewall of the dielectric layer and a sidewall of the second semiconductor layer. An epitaxy is performed to grow an epitaxy semiconductor region from the first semiconductor layer. The spacer is removed.
    Type: Application
    Filed: January 13, 2020
    Publication date: May 14, 2020
    Inventors: Kuo-Cheng Chiang, Shi Ning Ju, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
  • Publication number: 20200152666
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first fin active region of a first semiconductor material disposed within the first region, oriented in a first direction, wherein the first fin active region has a <100> crystalline direction along the first direction; and a second fin active region of a second semiconductor material disposed within the second region and oriented in the first direction, wherein the second fin active region has a <110> crystalline direction along the first direction.
    Type: Application
    Filed: January 13, 2020
    Publication date: May 14, 2020
    Inventors: Tzer-Min Shen, Zhiqiang Wu, Chung-Cheng Wu, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang, Min Cao
  • Publication number: 20200135578
    Abstract: Examples of an integrated circuit with an interconnect structure that includes a buried interconnect conductor and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a substrate that includes a plurality of fins extending from a remainder of the substrate. A spacer layer is formed between the plurality of fins, and a buried interconnect conductor is formed on the spacer layer between the plurality of fins. A set of capping layers is formed on the buried interconnect conductor between the plurality of fins. A contact recess is etched through the set of capping layers that exposes the buried interconnect conductor, and a contact is formed in the contact recess that is electrically coupled to the buried interconnect conductor.
    Type: Application
    Filed: February 28, 2019
    Publication date: April 30, 2020
    Inventors: Kuo-Cheng Ching, Shi Ning Ju, Kuan-Lun Cheng, Chih-Hao Wang
  • Publication number: 20200135890
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes device fins formed on a substrate; fill fins formed on the substrate and disposed among the device fins; and gate stacks formed on the device fins and the fill fins. The fill fins include a first dielectric material layer and a second dielectric material layer deposited on the first dielectric material layer. The first and second dielectric material layers are different from each other in composition.
    Type: Application
    Filed: December 30, 2019
    Publication date: April 30, 2020
    Inventors: Kuo-Cheng Chiang, Teng-Chun Tsai, Kuan-Lun Cheng, Chih-Hao Wang
  • Publication number: 20200135883
    Abstract: A FinFET device structure is provided. The FinFET device structure includes a fin structure formed over a substrate, and a gate structure formed over the fin structure. The FinFET device structure also includes an epitaxial source/drain (S/D) structure formed over the fin structure. A top surface and a sidewall of the fin structure are surrounded by the epitaxial S/D structure. A first distance between an outer surface of the epitaxial S/D structure and the sidewall of the fin structure is no less than a second distance between the outer surface of the epitaxial S/D structure and the top surface of the fin structure.
    Type: Application
    Filed: January 25, 2019
    Publication date: April 30, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sai-Hooi YEONG, Chi-On CHUI, Bo-Feng YOUNG, Bo-Yu LAI, Kuan-Lun CHENG, Chih-Hao WANG
  • Publication number: 20200135572
    Abstract: A method for fabricating a semiconductor device having a dielectric footing region includes forming a plurality of fin elements extending from a substrate. In some embodiments, a dielectric layer is deposited over each of the plurality of fin elements. After depositing the dielectric layer, a dummy gate electrode is formed over the plurality of fin elements and over the dielectric layer. In some examples, and after forming the dummy gate electrode, a first spacer layer is formed on opposing sidewalls of the dummy gate electrode and over the dielectric layer. In various embodiments, the dielectric layer extends laterally beneath the first spacer layer on each of the opposing sidewalls of the dummy gate electrode to provide the dielectric footing region.
    Type: Application
    Filed: June 21, 2019
    Publication date: April 30, 2020
    Inventors: Cheng-Ting CHUNG, Ching-Wei TSAI, Kuan-Lun CHENG
  • Publication number: 20200135634
    Abstract: A method includes etching a semiconductor substrate to form two semiconductor strips. The two semiconductor strips are over a bulk portion of the semiconductor substrate. The method further includes etching the bulk portion to form a trench in the bulk portion of the semiconductor substrate, forming a liner dielectric layer lining the trench, forming a buried contact in the trench, forming a buried power rail over and connected to the buried contact, wherein the buried power rail is between the two semiconductor strips, and forming isolation regions on opposite sides of the two semiconductor strips. The buried power rail is underlying a portion of the isolation regions.
    Type: Application
    Filed: March 6, 2019
    Publication date: April 30, 2020
    Inventors: Kuo-Cheng Chiang, Shi Ning Ju, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 10636910
    Abstract: A semiconductor device is provided, which includes a substrate, a fin structure, a capping layer and an oxide layer. The substrate has a well. The fin structure extends from the well. The capping layer surrounds a top surface and side surfaces of the fin structure. The oxide layer is over the substrate and covers the capping layer. A thickness of a top portion of the oxide layer above the capping layer is greater than a thickness of a sidewall portion of the oxide layer.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: April 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Ching, Kuan-Ting Pan, Kuan-Lun Cheng, Chih-Hao Wang