Patents by Inventor Kuang-Hsin Chen

Kuang-Hsin Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200227316
    Abstract: An apparatus includes a plurality of interconnect structures over a substrate, a dielectric layer formed over a top metal line of the plurality of interconnect structures, a first barrier layer on a bottom and sidewalls of an opening in the dielectric layer, wherein the first barrier layer is formed of a first material and has a first thickness, a second barrier layer over the first barrier layer, wherein the second barrier layer is formed of a second material different from the first material and has a second thickness and a pad over the second barrier layer, wherein the pad is formed of a third material.
    Type: Application
    Filed: March 26, 2020
    Publication date: July 16, 2020
    Inventors: Bor-Zen Tien, Jhu-Ming Song, Hsuan-Han Lin, Kuang-Hsin Chen, Mu-Yi Lin, Tzong-Sheng Chang
  • Publication number: 20200144130
    Abstract: In an embodiment, a FinFET device includes a semiconductor substrate and forming fins of a first height and a second height. A dielectric layer extends a fin of the first height to the fin of a second height. The dielectric layer is disposed on the top surface of the fin of the second height.
    Type: Application
    Filed: December 27, 2019
    Publication date: May 7, 2020
    Inventors: Joanna Chaw Yane YIN, Chi-Hsi WU, Kuo-Chiang TING, Kuang-Hsin CHEN
  • Publication number: 20200134810
    Abstract: The present disclosure provides a method and a system for scanning wafer. The system captures a defect image of a wafer, and generates a reference image corresponding to the first defect image based on a reference image generation model. The system generates a defect marked image based on the defect image and the reference image.
    Type: Application
    Filed: February 26, 2019
    Publication date: April 30, 2020
    Inventors: PEI-HSUAN LEE, CHIEN-HSIANG HUANG, KUANG-SHING CHEN, KUAN-HSIN CHEN, CHUN-CHIEH CHIN
  • Publication number: 20200135470
    Abstract: The present disclosure describes a system and a method for a ion implantation (IMP) process. The system includes an ion implanter configured to scan an ion beam over a target for a range of angles, a tilting mechanism configured to support and tilt the target, an ion-collecting device configured to collect a distribution and a number of ejected ions from the ion beam scan over the target, and a control unit configured to adjust a tilt angle based on a correction angle determined based on the distribution and number of ejected ions.
    Type: Application
    Filed: April 11, 2019
    Publication date: April 30, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Jung HUANG, Li-Hsin CHU, Po-Feng TSAI, Henry PENG, Kuang Huan HSU, Tsung Wei CHEN, Yung-Lin HSU
  • Patent number: 10629481
    Abstract: An apparatus includes a plurality of interconnect structures over a substrate, a dielectric layer formed over a top metal line of the plurality of interconnect structures, a first barrier layer on a bottom and sidewalls of an opening in the dielectric layer, wherein the first barrier layer is formed of a first material and has a first thickness, a second barrier layer over the first barrier layer, wherein the second barrier layer is formed of a second material different from the first material and has a second thickness and a pad over the second barrier layer, wherein the pad is formed of a third material.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: April 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bor-Zen Tien, Jhu-Ming Song, Hsuan-Han Lin, Kuang-Hsin Chen, Mu-Yi Lin, Tzong-Sheng Chang
  • Patent number: 10546786
    Abstract: In an embodiment, a method for fabricating a FinFET device includes providing a semiconductor substrate, etching the semiconductor substrate to form dummy fins and active fins. The group of dummy fins is etched through a patterned mask layer. An isolation feature is formed on the semiconductor substrate after etching the first group of dummy fins.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: January 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Joanna Chaw Yane Yin, Chi-Hsi Wu, Kuo-Chiang Ting, Kuang-Hsin Chen
  • Patent number: 10361085
    Abstract: A method for forming a semiconductor device structure is provided that includes forming an oxide layer over a substrate and forming a semiconductor layer over the oxide layer. The method includes patterning the semiconductor layer to form a fin structure over the oxide layer and removing a portion of the fin structure to form a U-shaped trench in the fin structure. The method also includes forming a gate structure on the U-shaped trench.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: July 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Chieh Lai, Kuang-Hsin Chen, Yung-Chun Wu, Mu-Shih Yeh
  • Patent number: 10347766
    Abstract: Embodiments of the present disclosure relate generally to a semiconductor device and method of fabricating the same, the semiconductor device includes a semiconductor substrate and a gate stack disposed over a channel region of the semiconductor device, the gate stack includes an oxidation layer, a gate dielectric and a gate electrode, the oxidation layer at least covers a portion of the channel region of the semiconductor device and may act as a barrier to prevent damage to the underlying features, such as the source and drain regions, during removal of a dummy gate in a gate last process.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: July 9, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Shuo Ho, Chia-Ming Chang, Tsung-Yu Chiang, Kuang-Hsin Chen, Bor-Zen Tien
  • Publication number: 20190189793
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a gate structure formed over the substrate; a source region and a drain region formed in the substrate on either side of the gate structure, the source region and the drain region both having a first type of conductivity; and a field plate formed over the substrate between the gate structure and the drain region; wherein the field plate is coupled to the source region or a bulk electrode of the substrate. An associated method for fabricating the semiconductor structure is also disclosed.
    Type: Application
    Filed: February 12, 2019
    Publication date: June 20, 2019
    Inventors: CHIH-CHANG CHENG, FU-YU CHU, RUEY-HSIN LIU, KUANG-HSIN CHEN, CHIH-HSIN KO, SHIH-FEN HUANG
  • Patent number: 10319675
    Abstract: The present disclosure provides one embodiment of a semiconductor structure that includes an interconnection structure formed on a semiconductor substrate; and a capacitor disposed in the interconnection structure. The interconnection structure includes a top electrode; a bottom electrode; a dielectric material layer sandwiched between the top and bottom electrodes; and a nanocrystal layer embedded in the dielectric material layer.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: June 11, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Chieh Lai, Meng-Ting Yu, Yung-Hsien Wu, Kuang-Hsin Chen
  • Patent number: 10249562
    Abstract: A method for fabricating a package structure is provided, which includes the steps of: providing a carrier having a recess; disposing an electronic element in the recess of the carrier; forming an insulating layer in the recess to encapsulate the electronic element; forming a circuit structure on the carrier, wherein the circuit structure is electrically connected to the electronic element; forming a plurality of through holes penetrating the carrier; and forming a conductive material in the through holes to form a plurality of conductors, wherein the conductors are electrically connected to the circuit structure. By using the carrier as a substrate body, the present invention avoids warping of the package structure.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: April 2, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Ching-Wen Chiang, Kuang-Hsin Chen, Hsien-Wen Chen
  • Publication number: 20190096766
    Abstract: Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. An etch sequence is performed to form a first etched region over a planar region of a semiconductor arrangement. The first etched region exposes a planar structure, such as an alignment mark used for alignment during semiconductor fabrication. The etch sequence forms a second etched region over a semiconductor fin region of the semiconductor arrangement. In an embodiment, the etch sequence forms a first trench, a first fin nub and a first pillar in the semiconductor fin region, where the first trench is formed in a semiconductor substrate of the semiconductor fin region. A multi-depth STI structure is formed over at least one of the first trench, the first fin nub, or the first pillar.
    Type: Application
    Filed: November 30, 2018
    Publication date: March 28, 2019
    Inventors: Tsung-Yu CHIANG, Kuang-Hsin CHEN, Hsin-Lung CHAO, Chen CHU-HSUAN
  • Publication number: 20190057908
    Abstract: In an embodiment, a method for fabricating a FinFET device includes providing a semiconductor substrate, etching the semiconductor substrate to form dummy fins and active fins. The group of dummy fins is etched through a patterned mask layer. An isolation feature is formed on the semiconductor substrate after etching the first group of dummy fins.
    Type: Application
    Filed: August 24, 2018
    Publication date: February 21, 2019
    Inventors: Joanna Chaw Yane YIN, Chi-Hsi WU, Kuo-Chiang TING, Kuang-Hsin CHEN
  • Patent number: 10205024
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a gate structure formed over the substrate; a source region and a drain region formed in the substrate on either side of the gate structure, the source region and the drain region both having a first type of conductivity; and a field plate formed over the substrate between the gate structure and the drain region; wherein the field plate is coupled to the source region or a bulk electrode of the substrate. An associated method for fabricating the semiconductor structure is also disclosed.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: February 12, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chih-Chang Cheng, Fu-Yu Chu, Ruey-Hsin Liu, Kuang-Hsin Chen, Chih-Hsin Ko, Shih-Fen Huang
  • Patent number: 10199320
    Abstract: A method of fabricating an electronic package is provided, including: providing a carrier body having a first surface formed with a plurality of recessed portions, and a second surface opposing the first surface and interconnecting with the recessed portions; forming on the first surface of the carrier body an electronic structure that has a plurality of conductive elements received in the recessed portions correspondingly; and removing portion of the carrier body, with the conductive elements exposed from the second surface of the carrier body. Therefore, the carrier body is retained, and the fabrication cost is reduced since temporary material is required. The present invention further provides the electronic package thus fabricated.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: February 5, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Ching-Wen Chiang, Kuang-Hsin Chen, Sheng-Li Lu, Hsien-Wen Chen
  • Patent number: 10177036
    Abstract: Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. An etch sequence is performed to form a first etched region over a planar region of a semiconductor arrangement. The first etched region exposes a planar structure, such as an alignment mark used for alignment during semiconductor fabrication. The etch sequence forms a second etched region over a semiconductor fin region of the semiconductor arrangement. In an embodiment, the etch sequence forms a first trench, a first fin nub and a first pillar in the semiconductor fin region, where the first trench is formed in a semiconductor substrate of the semiconductor fin region. A multi-depth STI structure is formed over at least one of the first trench, the first fin nub, or the first pillar.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: January 8, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Tsung-Yu Chiang, Kuang-Hsin Chen, Hsin-Lung Chao, Chen Chu-Hsuan
  • Patent number: 10163516
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a gate stack over the semiconductor substrate. The gate stack includes a first insulating layer, a charge trapping structure, a second insulating layer, and a gate electrode. The first insulating layer separates the semiconductor substrate from the charge trapping structure. The charge trapping structure is between the first insulating layer and the second insulating layer. The gate electrode is over the second insulating layer. The charge trapping structure includes a first layer and a second layer. The first layer includes zinc oxide, tin dioxide, titanium oxide, zinc tin oxide, indium oxide, indium zinc oxide, indium gallium zinc oxide, zinc oxynitride, tin oxynitride, titanium oxynitride, zinc tin oxynitride, indium oxynitride, indium zinc oxynitride, or indium gallium zinc oxynitride.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: I-Chen Huang, Kuang-Hsin Chen, Yung-Hsien Wu, Wen-Chao Shen
  • Publication number: 20180337123
    Abstract: The present disclosure provides one embodiment of a semiconductor structure that includes an interconnection structure formed on a semiconductor substrate; and a capacitor disposed in the interconnection structure. The interconnection structure includes a top electrode; a bottom electrode; a dielectric material layer sandwiched between the top and bottom electrodes; and a nanocrystal layer embedded in the dielectric material layer.
    Type: Application
    Filed: July 27, 2018
    Publication date: November 22, 2018
    Inventors: Cheng-Chieh Lai, Meng-Ting Yu, Yung-Hsien Wu, Kuang-Hsin Chen
  • Publication number: 20180337248
    Abstract: A semiconductor device and method of manufacturing same are described. A first hafnium oxide (HfO2) layer is formed on a substrate. A titanium (Ti) layer is formed over the first hafnium oxide layer. A second hafnium oxide layer is formed over the titanium layer. The composite device structure is thermally annealed to produce a high-k dielectric structure having a hafnium titanium oxide (HfxTi1-xO2) layer interposed between the first hafnium oxide layer and the second hafnium oxide layer.
    Type: Application
    Filed: July 31, 2018
    Publication date: November 22, 2018
    Inventors: I-Chen Huang, Yi-Ju Hsu, Chi-Wen Liu, Kuang-Hsin Chen, Yung-Hsien Wu, Chin-Yu Chen
  • Patent number: 10134626
    Abstract: A semiconductor device is provided. The semiconductor device includes a doped isolation structure formed above a substrate, and the doped isolation structure includes a first doped portion and a second doped portion, and a doped concentration of the second doped portion is different from a doped concentration of the first doped portion. The semiconductor device also includes a first fin partially embedded in the doped isolation structure, and a sidewall surface of the first fin is in direct contact with the first doped portion. The semiconductor device includes a second fin partially embedded in the doped isolation structure, and the doped isolation structure is between the first fin and the second fin, and a sidewall surface of the second fin is in direct contact with the second doped portion.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: November 20, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsung-Yu Chiang, Chung-Wei Lin, Kuang-Hsin Chen, Bor-Zen Tien