Patents by Inventor Kuang-Hsiung Chen

Kuang-Hsiung Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8143101
    Abstract: The present invention relates to semiconductor package and the method of making the same. The method of the invention comprises the following steps: (a) providing a first substrate; (b) mounting a first chip onto a surface of the first substrate; (c) forming a plurality of conductive elements on the surface of the first substrate; (d) covering the conductive elements with a mold, the mold having a plurality of cavities accommodating top ends of each of the conductive elements; and (e) forming a first molding compound for encapsulating the surface of the first substrate, the first chip and parts of the conductive elements, wherein the height of the first molding compound is smaller than the height of each of the conductive elements. Thus, the first molding compound encapsulates the entire surface of the first substrate, so that the mold flush of the first molding compound will not occur, and the rigidity of the first substrate is increased.
    Type: Grant
    Filed: March 21, 2008
    Date of Patent: March 27, 2012
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Yu-Ching Sun, Ren-Yi Cheng, Tsai Wan, Chih-Hung Hsu, Kuang-Hsiung Chen
  • Publication number: 20120049338
    Abstract: In one embodiment, a semiconductor device package includes: (1) a substrate unit; (2) connecting elements disposed adjacent to a periphery of the substrate unit and extending upwardly from an upper surface of the substrate unit; (3) a semiconductor device disposed adjacent to the upper surface of the substrate unit and electrically connected to the substrate unit; and (4) a package body disposed adjacent to the upper surface of the substrate unit and covering the semiconductor device. A lateral surface of the package body is substantially aligned with a lateral surface of the substrate unit. The package body defines openings that at least partially expose respective ones of the connecting elements. At least one of the connecting elements has a width WC, and at least one of the openings has a width WU adjacent to an upper surface of the package body, such that WU>WC.
    Type: Application
    Filed: November 7, 2011
    Publication date: March 1, 2012
    Inventors: Kuang-Hsiung Chen, Chi-Chih Shen, Jen-Chuan Chen, Wen-Hsiung Chang, Hui-Shan Chang, Pei-Yu Hsu, Fa-Hao Wu, Chen-Yu Chia, Chi-Chih Chu, Cheng-Yi Weng, Ya-Wen Hsu
  • Patent number: 8076765
    Abstract: In one embodiment, a semiconductor device package includes: (1) a substrate unit; (2) connecting elements disposed adjacent to a periphery of the substrate unit and extending upwardly from an upper surface of the substrate unit; (3) a semiconductor device disposed adjacent to the upper surface of the substrate unit and electrically connected to the substrate unit; and (4) a package body disposed adjacent to the upper surface of the substrate unit and covering the semiconductor device. A lateral surface of the package body is substantially aligned with a lateral surface of the substrate unit. The package body defines openings that at least partially expose respective ones of the connecting elements. At least one of the connecting elements has a width WC, and at least one of the openings has a width WU adjacent to an upper surface of the package body, such that WU>WC.
    Type: Grant
    Filed: July 22, 2009
    Date of Patent: December 13, 2011
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Kuang-Hsiung Chen, Chi-Chih Shen, Jen-Chuan Chen, Wen-Hsiung Chang, Hui-Shan Chang, Pei-Yu Hsu, Fa-Hao Wu, Chen-Yu Chia, Chi-Chih Chu, Cheng-Yi Weng, Ya-Wen Hsu
  • Patent number: 8058725
    Abstract: A package structure and a package substrate thereof are provided. The package structure includes a package substrate, a chip and a molding compound. The package substrate has an upper surface and a lower surface. The lower surface has a molding area and a pad area. The molding area has at least one window opening penetrating the upper surface and the lower surface. The pad area is used for disposing at least one solder ball or at least one connecting pin. The package substrate includes a solder mask. The solder mask covers the lower surface of the package substrate. The solder mask has at least one groove. The groove is disposed between the molding area and the pad area. The chip disposed on the package substrate has an active surface. The active surface contacts with the upper surface of the package substrate. The molding area is covered by the molding compound.
    Type: Grant
    Filed: October 10, 2007
    Date of Patent: November 15, 2011
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Kuang-Hsiung Chen, Chen-Ming Cheng, Hung-Ju Chung
  • Publication number: 20110169150
    Abstract: A semiconductor package includes a substrate unit, a die electrically connected to first contact pads, and a package body covering a first patterned conductive layer and the die. The substrate unit includes: (1) the first patterned conductive layer; (2) a first dielectric layer exposing a part of the first patterned conductive layer to form the first contact pads; (3) a second patterned conductive layer; (4) a second dielectric layer defining openings extending from the first patterned conductive layer to the second patterned conductive layer, where the second patterned conductive layer includes second contact pads exposed by the second dielectric layer; and (5) conductive posts extending from the first patterned conductive layer to the second contact pads through the openings, each of the conductive posts filling a corresponding one of the openings. At least one of the conductive posts defines a cavity.
    Type: Application
    Filed: January 13, 2011
    Publication date: July 14, 2011
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yuan-Chang Su, Shih-Fu Huang, Chia-Cheng Chen, Tzu-Hui Chen, Kuang-Hsiung Chen, Pao-Ming Hsieh, Ming Chiang Lee, Bernd Karl Appelt
  • Patent number: 7927924
    Abstract: The present invention relates to a semi-finished package and a method for making a package. The semi-finished package includes a carrier and at least one molding compound. The molding compound is disposed on a surface of the carrier, and has a body and a plurality of outer protrusions. The outer protrusions are disposed at the periphery of the body, and the height of the outer protrusions is greater than that of the body. Thus, by utilizing the outer protrusions, the rigidity of the semi-finished package is increased, so as to overcome the warpage of the semi-finished package caused by different coefficients of thermal expansion of the molding compound and the carrier. Therefore, the yield rate of the package unit is increased.
    Type: Grant
    Filed: April 30, 2009
    Date of Patent: April 19, 2011
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Ren-Yi Cheng, Kuang-Hsiung Chen, Chun-Hung Hsu
  • Publication number: 20110084370
    Abstract: A package carrier includes: (a) a dielectric layer defining a plurality of openings; (b) patterned electrically conductive layer, embedded in the dielectric layer and disposed adjacent to a first surface of the dielectric layer; a plurality of electrically conductive posts, disposed in respective ones of the openings, wherein the openings extend between a second surface of the dielectric layer to the patterned electrically conductive layer, the electrically conductive posts a connected to the patterned electrically conductive layer, and an end of each of the electrically conductive posts has a curved profile and is faced away from the patterned electrically conductive layer; and (d) a patterned solder resist layer, disposed adjacent to the first surface of the dielectric layer and exposing portions of the patterned electrically conductive layer corresponding to contact pads. A semiconductor package includes the package carrier, a chip, and an encapsulant covering the chip and the package carrier.
    Type: Application
    Filed: October 14, 2010
    Publication date: April 14, 2011
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: YUAN-CHANG SU, SHIH-FU HUANG, CHIA-CHENG CHEN, CHIA-HSIUNG HSIEH, TZU-HUI CHEN, KUANG-HSIUNG CHEN, PAO-MING HSIEH
  • Publication number: 20110062567
    Abstract: A leadframe including a die pad, leads, an outer frame, connecting bars and grounding bars is provided. Each of the grounding bars is suspended between two connecting bars by being connected with branches of the two connecting bars, such that the grounding bars are spaced by the die pad. The leadframe and the chip package of the present invention can permit a great design variation.
    Type: Application
    Filed: August 19, 2010
    Publication date: March 17, 2011
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yueh-Chen Hsu, Mei-Lin Hsieh, Chih-Hung Hsu, Kuang-Hsiung Chen, Yi-Cheng Hsu
  • Publication number: 20110057301
    Abstract: A semiconductor package includes a patterned metal foil, a chip, wires, a patterned dielectric layer, an adhesive layer, and a molding compound. The patterned metal foil has a first surface and a second surface opposite thereto. The patterned dielectric layer is disposed on the second surface and has openings exposing at least a portion of the patterned metal foil to form joints for external electrical connection. The chip is disposed on the first surface. The adhesive layer is disposed between the chip and the patterned metal foil. The wires respectively connect the chip and the patterned metal foil. The patterned dielectric layer is located below intersections between the wires and the patterned metal foil. The patterned dielectric layer, the wires, and the patterned metal foil overlap with one another on a plane. The molding compound is disposed on the first surface and covers the chip and the wires.
    Type: Application
    Filed: October 28, 2009
    Publication date: March 10, 2011
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Kuang-Hsiung Chen, Pao-Ming Hsieh, Yuan-Chang Su, Shih-Fu Huang, Bernd Karl Appelt
  • Publication number: 20110049704
    Abstract: In one embodiment, a semiconductor device package includes a circuit substrate, a chip, a plurality of first solder balls, an encapsulant, and a heatsink. The circuit substrate includes a carrying surface and a plurality of first bonding pads thereon. The chip is disposed on the carrying surface and electrically connected to the circuit substrate. The first bonding pads are located outside of the chip. The first solder balls are disposed on the first bonding pads. The encapsulant is disposed on the carrying surface and covers the chip. The encapsulant includes a plurality of openings exposing the first solder balls. The heatsink is disposed over the encapsulant and bonded to the first solder balls, wherein the heatsink includes a plurality of protrusions on a bonding surface facing the encapsulant, and the protrusions are correspondingly embedded into the first solder balls.
    Type: Application
    Filed: April 29, 2010
    Publication date: March 3, 2011
    Inventors: Yu-Ching Sun, Fa-Hao Wu, Kuang-Hsiung Chen
  • Publication number: 20100320610
    Abstract: A semiconductor package includes a substrate, a die, and a package body. The substrate includes: (a) a core including a resin reinforced with fibers; (b) a plurality of openings extending through the core; (c) a dielectric layer; and (d) a single conductive layer disposed between the dielectric layer and the core. Portions of a lower surface of the single conductive layer cover the plurality of openings to form a plurality of first contact pads for electrical connection external to the semiconductor package. Exposed portions of an upper surface of the single conductive layer form a plurality of second contact pads. The die is electrically connected to the plurality of second contact pads, and the package body encapsulates the die.
    Type: Application
    Filed: May 13, 2010
    Publication date: December 23, 2010
    Inventors: SHIH-FU HUANG, Yuan-Chang Su, Chia-Cheng Chen, Kuang-Hsiung Chen, Ming-Chiang Lee, Bernd Karl Appelt, Chia-Hsiung Hsieh
  • Publication number: 20100314744
    Abstract: A chip package structure includes a substrate, a die, and a package body. The substrate includes a single patterned, electrically conductive layer, and a patterned dielectric layer adjacent to an upper surface of the electrically conductive layer. A part of a lower surface of the electrically conductive layer forms first contact pads for electrical connection externally. The patterned dielectric layer exposes a part of the upper surface of the electrically conductive layer to form second contact pads. The electrically conductive layer exposes the lower surface of the patterned dielectric layer on a lower periphery of the substrate. The die is electrically connected to the second contact pads, the patterned dielectric layer and the die being positioned on the same side of the electrically conductive layer. The package body is disposed adjacent to the upper surface of the electrically conductive layer and covers the patterned dielectric layer and the die.
    Type: Application
    Filed: May 13, 2010
    Publication date: December 16, 2010
    Inventors: Shih-Fu Huang, Yuan-Chang Su, Chia-Cheng Chen, Ta-Chun Lee, Kuang-Hsiung Chen
  • Publication number: 20100171205
    Abstract: In one embodiment, a semiconductor device package includes: (1) a substrate unit; (2) connecting elements disposed adjacent to a periphery of the substrate unit and extending upwardly from an upper surface of the substrate unit; (3) a semiconductor device disposed adjacent to the upper surface of the substrate unit and electrically connected to the substrate unit; and (4) a package body disposed adjacent to the upper surface of the substrate unit and covering the semiconductor device. A lateral surface of the package body is substantially aligned with a lateral surface of the substrate unit. The package body defines openings that at least partially expose respective ones of the connecting elements. At least one of the connecting elements has a width WC, and at least one of the openings has a width WU adjacent to an upper surface of the package body, such that WU>WC.
    Type: Application
    Filed: July 22, 2009
    Publication date: July 8, 2010
    Inventors: Kuang-Hsiung CHEN, Chi-Chih SHEN, Jen-Chuan CHEN, Wen-Hsiung CHANG, Hui-Shan CHANG, Pei-Yu HSU, Fa-Hao WU, Chen-Yu CHIA, Chi-Chih CHU, Cheng-Yi WENG, Ya-Wen HSU
  • Publication number: 20090278253
    Abstract: The present invention relates to a semi-finished package and a method for making a package. The semi-finished package includes a carrier and at least one molding compound. The molding compound is disposed on a surface of the carrier, and has a body and a plurality of outer protrusions. The outer protrusions are disposed at the periphery of the body, and the height of the outer protrusions is greater than that of the body. Thus, by utilizing the outer protrusions, the rigidity of the semi-finished package is increased, so as to overcome the warpage of the semi-finished package caused by different coefficients of thermal expansion of the molding compound and the carrier. Therefore, the yield rate of the package unit is increased.
    Type: Application
    Filed: April 30, 2009
    Publication date: November 12, 2009
    Inventors: Ren-Yi Cheng, Kuang-Hsiung Chen, Chun-Hung Hsu
  • Publication number: 20090252931
    Abstract: A reinforced assembly carrier is provided. A supporting frame made of molding compound is formed on the edge area of the upper surface and/or on the edge area of the lower surface of the assembly carrier thereby enhancing the mechanical strength of the assembly carrier.
    Type: Application
    Filed: June 9, 2008
    Publication date: October 8, 2009
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING INC.
    Inventors: Ren Yih JENG, Kuang Hsiung CHEN, Chun Hung HSU
  • Publication number: 20080230882
    Abstract: A chip package structure includes a die pad of which at least a notch is formed on at least one side and opposite to a mold gate. The die pad contributes to accelerating the injection of an encapsulating material, so as to exhaust the air in the mold in time, before the encapsulating material solidifies during the molding step, thereby overcoming or at least improving the problem of defects such as air bubbles in the encapsulation.
    Type: Application
    Filed: March 19, 2008
    Publication date: September 25, 2008
    Inventors: Mei-Lin Hsieh, Chih-Hung Hsu, Kuang-Hsiung Chen
  • Publication number: 20080230887
    Abstract: The present invention relates to semiconductor package and the method of making the same. The method of the invention comprises the following steps: (a) providing a first substrate; (b) mounting a first chip onto a surface of the first substrate; (c) forming a plurality of conductive elements on the surface of the first substrate; (d) covering the conductive elements with a mold, the mold having a plurality of cavities accommodating top ends of each of the conductive elements; and (e) forming a first molding compound for encapsulating the surface of the first substrate, the first chip and parts of the conductive elements, wherein the height of the first molding compound is smaller than the height of each of the conductive elements. Thus, the first molding compound encapsulates the entire surface of the first substrate, so that the mold flush of the first molding compound will not occur, and the rigidity of the first substrate is increased.
    Type: Application
    Filed: March 21, 2008
    Publication date: September 25, 2008
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yu-Ching Sun, Ren-Yi Cheng, Tsai Wan, Chih-Hung Hsu, Kuang-Hsiung Chen
  • Publication number: 20080185698
    Abstract: A semiconductor package structure is disclosed. The structure comprises a die pad, a chip, leads, a recess, and an encapsulant. The chip is disposed on the die pad. The leads are disposed on a periphery of the die pad and electrically connected to the chip. The recess is formed on the top surface of at least one of the leads and extends to the outside surface thereof. The encapsulant is used for encapsulating the die pad, the chip, the leads, and the recess.
    Type: Application
    Filed: November 19, 2007
    Publication date: August 7, 2008
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yen-Wen Tseng, Mei-Lin Hsieh, Chih-Hung Hsu, Kuang-Hsiung Chen
  • Publication number: 20080105974
    Abstract: A package structure and a package substrate thereof are provided. The package structure includes a package substrate, a chip and a molding compound. The package substrate has an upper surface and a lower surface. The lower surface has a molding area and a pad area. The molding area has at least one window opening penetrating the upper surface and the lower surface. The pad area is used for disposing at least one solder ball or at least one connecting pin. The package substrate includes a solder mask. The solder mask covers the lower surface of the package substrate. The solder mask has at least one groove. The groove is disposed between the molding area and the pad area. The chip disposed on the package substrate has an active surface. The active surface contacts with the upper surface of the package substrate. The molding area is covered by the molding compound.
    Type: Application
    Filed: October 10, 2007
    Publication date: May 8, 2008
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Kuang-Hsiung Chen, Chen-Ming Cheng, Hung-Ju Chung
  • Publication number: 20040233637
    Abstract: The invention provides a slim type packaging structure with high heat dissipation, which is to provide a hole on the surface of a substrate, and then a die is placed inside the hole. Besides, a plurality of wire is separately connected from the die to the substrate. Alternatively, a heat-dissipating panel with good conductivity can be placed inside the hole, and then the die is placed on the heat-dissipating panel. Thus, after the substrate is soldered on the circuit board, a direct heat-dissipating path can be formed between the die and the circuit board; therefore, the die can dissipate heat without passing through the substrate. Hence, the slim type packaging structure with high heat dissipation provided by the invention can achieve double effects of good heat dissipation and package volume slimming as well as have the advantages of low cost and simple design.
    Type: Application
    Filed: May 20, 2003
    Publication date: November 25, 2004
    Inventors: Kuang-Hsiung Chen, Wen-Chi Chiang, Ji-Ming Li, Wai-Chih Liu, Tien-Tzu Su