Patents by Inventor Kuei-Liang Lu

Kuei-Liang Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200212217
    Abstract: A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region.
    Type: Application
    Filed: December 24, 2019
    Publication date: July 2, 2020
    Inventors: Shao-Ming YU, Chang-Yun CHANG, Chih-Hao CHANG, Hsin-Chih CHEN, Kai-Tai CHANG, Ming-Feng SHIEH, Kuei-Liang LU, Yi-Tang LIN
  • Publication number: 20200125784
    Abstract: An integrated circuit device includes first and second features, each including an end portion arranged along a common axis, and separated by a space. The end portion of the first feature includes a first indention adjacent to the space. The end portion of the second feature includes a first indention adjacent to the space, mirroring the first indention of the first feature about the space. The end portions are substantially similar in shape.
    Type: Application
    Filed: December 18, 2019
    Publication date: April 23, 2020
    Inventors: Shih-Ming Chang, Kuei-Liang Lu
  • Patent number: 10573751
    Abstract: A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: February 25, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shao-Ming Yu, Chang-Yun Chang, Chih-Hao Chang, Hsin-Chih Chen, Kai-Tai Chang, Ming-Feng Shieh, Kuei-Liang Lu, Yi-Tang Lin
  • Patent number: 10528693
    Abstract: An integrated circuit device includes first and second features, each including an end portion arranged along a common axis, and separated by a space. The end portion of the first feature includes a first indention adjacent to the space. The end portion of the second feature includes a first indention adjacent to the space, mirroring the first indention of the first feature about the space. The end portions are substantially similar in shape.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: January 7, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Ming Chang, Kuei-Liang Lu
  • Patent number: 10049885
    Abstract: A method for patterning fins for FinFET devices are disclosed. The method includes forming elongated protrusions on a semiconductor substrate and forming a mask covering a first portion of the elongated protrusions. The method further includes forming a spacer surrounding the mask. The mask and the spacer together cover a second portion of the elongated protrusions. The method further includes removing a portion of the elongated protrusions not covered by the mask and the spacer. In an embodiment, an outer boundary of the spacer and the mask corresponds to an outer boundary of a non-rectangular pattern.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: August 14, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hoi-Tou Ng, Kuei-Liang Lu, Ming-Feng Shieh, Ru-Gun Liu
  • Patent number: 9983473
    Abstract: A photomask and method for fabricating an integrated circuit is provided. A design layout is provided, wherein the design layout has a plurality of main features. A plurality of assistant features are added in an assistant region of the design layout to form a first layout, wherein the assistant region has no main feature and a width of the assistant region is larger than five times of a width of the main feature. A plurality of optical proximity correction (OPC) features are added on the first layout to form a second layout. And a photomask is formed according to the second layout.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: May 29, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Yu Lin, Yi-Jie Chen, Feng-Yuan Chiu, Ying-Chou Cheng, Kuei-Liang Lu, Ya-Hui Chang, Ru-Gun Liu, Tsai-Sheng Gau
  • Patent number: 9917192
    Abstract: A method includes forming an isolation feature in a semiconductor substrate; forming a first fin-like active region and a second fin-like active region in the semiconductor substrate and interposed by the isolation feature; forming a dummy gate stack on the isolation feature, wherein the dummy gate extends to the first fin-like active region from one side and to the second fin-like active region from another side.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: March 13, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shao-Ming Yu, Chang-Yun Chang, Chih-Hao Chang, Hsin-Chih Chen, Kai-Tai Chang, Ming-Feng Shieh, Kuei-Liang Lu, Yi-Tang Lin
  • Patent number: 9904163
    Abstract: Disclosed is a mask for use in a lithography system having a defined resolution. The mask comprises first and second patterns that are greater than the defined resolution and a sub-resolution feature that is less than the defined resolution. Portions of the first and second patterns are positioned close to each other and separated by the sub-resolution feature in an intersection area. The size and shape of the sub-resolution feature are such that when the mask is used in the lithography system, a resulting pattern includes the first and second patterns interconnected with each other through the interconnection area.
    Type: Grant
    Filed: January 8, 2016
    Date of Patent: February 27, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-De Ho, Ching-Yu Chang, Kuei-Liang Lu, Ming-Feng Shieh
  • Patent number: 9823574
    Abstract: A device for semiconductor fabrication includes a substrate and a layer formed over the substrate, wherein the layer includes an alignment mark. The alignment mark includes a first plurality of elongated members that are oriented lengthwise along a first direction and are distributed along a second direction. The alignment mark further includes a second plurality of elongated members that are oriented lengthwise along a third direction perpendicular to the first direction and are distributed along the second direction, wherein the second direction is different from each of the first and third directions.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: November 21, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ching-Huang Chen, Hung-Chang Hsieh, Kuei-Liang Lu, Ya Hui Chang, Spencer Lin
  • Patent number: 9805154
    Abstract: The present disclosure provides one embodiment of an IC method that includes receiving an IC design layout including a first main feature and inserting a first plurality of scattering bars in the IC design layout to form a first circular pattern of scattering bars around the first main feature. The first main feature is positioned at a center portion of the first circular pattern of scattering bars.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: October 31, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Irene Ho, Ai-Jen Hung, Hung-Chang Hsieh, Kuei-Liang Lu, Ya Hui Chang
  • Publication number: 20170271503
    Abstract: A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region.
    Type: Application
    Filed: June 5, 2017
    Publication date: September 21, 2017
    Inventors: Shao-Ming YU, Chang-Yun CHANG, Chih-Hao CHANG, Hsin-Chih CHEN, Kai-Tai CHANG, Ming-Feng SHIEH, Kuei-Liang LU, Yi-Tang LIN
  • Publication number: 20170160633
    Abstract: A photomask and method for fabricating an integrated circuit is provided. A design layout is provided, wherein the design layout has a plurality of main features. A plurality of assistant features are added in an assistant region of the design layout to form a first layout, wherein the assistant region has no main feature and a width of the assistant region is larger than five times of a width of the main feature. A plurality of optical proximity correction (OPC) features are added on the first layout to form a second layout. And a photomask is formed according to the second layout.
    Type: Application
    Filed: February 17, 2017
    Publication date: June 8, 2017
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Yu LIN, Yi-Jie CHEN, Feng-Yuan CHIU, Ying-Chou CHENG, Kuei-Liang LU, Ya-Hui CHANG, Ru-Gun LIU, Tsai-Sheng GAU
  • Patent number: 9673328
    Abstract: A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: June 6, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shao-Ming Yu, Chang-Yun Chang, Chih-Hao Chang, Hsin-Chih Chen, Kai-Tai Chang, Ming-Feng Shieh, Kuei-Liang Lu, Yi-Tang Lin
  • Publication number: 20170124243
    Abstract: An integrated circuit device includes first and second features, each including an end portion arranged along a common axis, and separated by a space. The end portion of the first feature includes a first indention adjacent to the space. The end portion of the second feature includes a first indention adjacent to the space, mirroring the first indention of the first feature about the space. The end portions are substantially similar in shape.
    Type: Application
    Filed: November 21, 2016
    Publication date: May 4, 2017
    Inventors: Shih-Ming Chang, Kuei-Liang Lu
  • Patent number: 9612526
    Abstract: A photomask and method for fabricating an integrated circuit is provided. The photomask includes a plurality of main features, enclosed in at least one first region and at least one second region, wherein the first region comprises single the main feature and the second region comprises multiple the main features; and a plurality of assistant features disposed between the first region and the second region, or between the second regions. The photomask enhances the accuracy of the critical dimension and facilitate fabricating an integrated circuit.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: April 4, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Yu Lin, Yi-Jie Chen, Feng-Yuan Chiu, Ying-Chou Cheng, Kuei-Liang Lu, Ya-Hui Chang, Ru-Gun Liu, Tsai-Sheng Gau
  • Publication number: 20170090299
    Abstract: A device for semiconductor fabrication includes a substrate and a layer formed over the substrate, wherein the layer includes an alignment mark. The alignment mark includes a first plurality of elongated members that are oriented lengthwise along a first direction and are distributed along a second direction. The alignment mark further includes a second plurality of elongated members that are oriented lengthwise along a third direction perpendicular to the first direction and are distributed along the second direction, wherein the second direction is different from each of the first and third directions.
    Type: Application
    Filed: September 29, 2015
    Publication date: March 30, 2017
    Inventors: Ching-Huang Chen, Hung-Chang Hsieh, Kuei-Liang Lu, Ya Hui Chang
  • Patent number: 9595440
    Abstract: A method of semiconductor device fabrication including placing a substrate having a first and second features disposed thereon in a vaporizing spray deposition system. An atomizing spray head of the vaporizing spray deposition system is used to deposit a conformal polymer layer on the first and second features. The first feature having the layer of the polymer disposed thereon and having a first width. A spray trim process is performed on the first and second features having the polymer layer disposed thereon using the atomizing spray head.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: March 14, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Yu Chang, Kuei-Liang Lu, Ming-Feng Shieh
  • Patent number: 9501601
    Abstract: A method for feature pattern modification includes extracting both a main pattern and a cut pattern from a design pattern, the main pattern being laid out under a set of process guidelines that improve the process window during formation of the main pattern, and modifying at least one of: the main pattern and the cut pattern if either feature pattern is in violation of a layout rule.
    Type: Grant
    Filed: October 21, 2013
    Date of Patent: November 22, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Ming Chang, Kuei-Liang Lu
  • Publication number: 20160335385
    Abstract: The present disclosure provides one embodiment of an IC method that includes receiving an IC design layout including a first main feature and inserting a first plurality of scattering bars in the IC design layout to form a first circular pattern of scattering bars around the first main feature. The first main feature is positioned at a center portion of the first circular pattern of scattering bars.
    Type: Application
    Filed: May 15, 2015
    Publication date: November 17, 2016
    Inventors: Irene Ho, Ai-Jen Hung, Hung-Chang Hsieh, Kuei-Liang Lu, Ya Hui Chang
  • Patent number: 9437415
    Abstract: Methods for aligning layers more accurately for FinFETs fabrication. An embodiment method includes forming a first pattern in a workpiece using a first photomask, forming a second pattern in the workpiece using a second photomask, the second photomask aligned to the first pattern, and aligning a third pattern to the first and the second patterns by aligning a first feature of the third pattern to a first feature of the first pattern in a first direction, and aligning a second feature of the third pattern to a first feature of the second pattern in a second direction orthogonal to the first direction.
    Type: Grant
    Filed: June 7, 2013
    Date of Patent: September 6, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Feng Shieh, Kuei-Liang Lu