Patents by Inventor Kuen-Ting Shiu

Kuen-Ting Shiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10756506
    Abstract: A semiconductor device including a substrate structure including a semiconductor material layer that is present directly on a buried dielectric layer in a first portion of the substrate structure and an isolation dielectric material that is present directly on the buried dielectric layer in a second portion of the substrate structure. The semiconductor device further includes a III-V optoelectronic device that is present in direct contact with the isolation dielectric material in a first region of the second portion of the substrate structure. A dielectric wave guide is present in direct contact with the isolation dielectric material in a second region of the second portion of the substrate structure.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: August 25, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Cheng-Wei Cheng, Ning Li, Devendra K. Sadana, Kuen-Ting Shiu
  • Patent number: 10686090
    Abstract: A photovoltaic device and method for fabrication include multijunction cells, each cell having a material grown independently from the other and including different band gap energies. An interface is disposed between the cells and configured to wafer bond the cells wherein the cells are configured to be adjacent without regard to lattice mismatch.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: June 16, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen W. Bedell, Cheng-Wei Cheng, Jeehwan Kim, Devendra K. Sadana, Kuen-Ting Shiu, Norma E. Sosa Cortes
  • Patent number: 10601199
    Abstract: A structure includes an optoelectronic device having a Group IV substrate (e.g., Si); a buffer layer (e.g. SiGe) disposed on the substrate and a first distributed Bragg reflector (DBR) disposed on the buffer layer. The first DBR contains alternating layers of doped Group IV materials (e.g., alternating layers of SiyGe(1-y), where 0.8<y<1, and SizGe(1-z), where 0.2<z<0.4) that are substantially transparent to a wavelength of interest. The structure further includes a strained layer of a Group III-V material over the first DBR and a second DBR over the strained layer. The second DBR contains alternating layers of electrically conductive oxides (e.g., ITO/AZO) that are substantially transparent to the wavelength of interest. Embodiments of VCSELs and photodetectors can be derived from the structure. The strained layer of Group III-V material can be, for example, a thin layer of In0.53Ga0.47As having a thickness in a range of about 2 nm to about 5 nm.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: March 24, 2020
    Assignee: International Business Machines Corporation
    Inventors: Cheng-Wei Cheng, Effendi Leobandung, Ning Li, Devendra K. Sadana, Kuen-Ting Shiu
  • Publication number: 20190363509
    Abstract: A semiconductor device including a substrate structure including a semiconductor material layer that is present directly on a buried dielectric layer in a first portion of the substrate structure and an isolation dielectric material that is present directly on the buried dielectric layer in a second portion of the substrate structure. The semiconductor device further includes a III-V optoelectronic device that is present in direct contact with the isolation dielectric material in a first region of the second portion of the substrate structure. A dielectric wave guide is present in direct contact with the isolation dielectric material in a second region of the second portion of the substrate structure.
    Type: Application
    Filed: August 7, 2019
    Publication date: November 28, 2019
    Inventors: Cheng-Wei Cheng, Ning Li, Devendra K. Sadana, Kuen-Ting Shiu
  • Patent number: 10460948
    Abstract: A method comprises providing a sacrificial release layer on a base substrate; forming a device layer on the sacrificial release layer; depositing a metal stressor layer on the device layer; etching the sacrificial release layer; and using epitaxial lift off to release the device layer and the metal stressor layer from the base substrate.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: October 29, 2019
    Assignee: International Business Machines Corporation
    Inventors: Cheng-Wei Cheng, Ning Li, Devendra K. Sadana, Kuen-Ting Shiu
  • Publication number: 20190312126
    Abstract: A lateral bipolar junction transistor including an emitter region, base region and collector region laterally orientated over a type IV semiconductor substrate, each of the emitter region, the base region and the collector region being composed of a type III-V semiconductor material. A buried oxide layer is present between the type IV semiconductor substrate and the emitter region, the base region and the collector region. The buried oxide layer having a pedestal aligned with the base region.
    Type: Application
    Filed: April 4, 2018
    Publication date: October 10, 2019
    Inventors: Kuen-Ting Shiu, Tak H. Ning, Jeng-Bang Yau, Cheng-Wei Cheng, Ko-Tao Lee
  • Patent number: 10439356
    Abstract: A semiconductor device including a substrate structure including a semiconductor material layer that is present directly on a buried dielectric layer in a first portion of the substrate structure and an isolation dielectric material that is present directly on the buried dielectric layer in a second portion of the substrate structure. The semiconductor device further includes a III-V optoelectronic device that is present in direct contact with the isolation dielectric material in a first region of the second portion of the substrate structure. A dielectric wave guide is present in direct contact with the isolation dielectric material in a second region of the second portion of the substrate structure.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: October 8, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Cheng-Wei Cheng, Ning Li, Devendra K. Sadana, Kuen-Ting Shiu
  • Publication number: 20190140424
    Abstract: A structure includes an optoelectronic device having a Group IV substrate (e.g., Si); a buffer layer (e.g. SiGe) disposed on the substrate and a first distributed Bragg reflector (DBR) disposed on the buffer layer. The first DBR contains alternating layers of doped Group IV materials (e.g., alternating layers of SiyGe(1-y), where 0.8<y<1, and SizGe(1-z), where 0.2<z<0.4) that are substantially transparent to a wavelength of interest. The structure further includes a strained layer of a Group III-V material over the first DBR and a second DBR over the strained layer. The second DBR contains alternating layers of electrically conductive oxides (e.g., ITO/AZO) that are substantially transparent to the wavelength of interest. Embodiments of VCSELs and photodetectors can be derived from the structure. The strained layer of Group III-V material can be, for example, a thin layer of In0.53Ga0.47As having a thickness in a range of about 2 nm to about 5 nm.
    Type: Application
    Filed: January 4, 2019
    Publication date: May 9, 2019
    Inventors: Cheng-Wei Cheng, Effendi Leobandung, Ning Li, Devendra K. Sadana, Kuen-Ting Shiu
  • Patent number: 10256608
    Abstract: A structure includes an optoelectronic device having a Group IV substrate (e.g., Si); a buffer layer (e.g. SiGe) disposed on the substrate and a first distributed Bragg reflector (DBR) disposed on the buffer layer. The first DBR contains alternating layers of doped Group IV materials (e.g., alternating layers of SiyGe(1-y), where 0.8<y<1, and SizGe(1-z), where 0.2<z<0.4) that are substantially transparent to a wavelength of interest. The structure further includes a strained layer of a Group III-V material over the first DBR and a second DBR over the strained layer. The second DBR contains alternating layers of electrically conductive oxides (e.g., ITO/AZO) that are substantially transparent to the wavelength of interest. Embodiments of VCSELs and photodetectors can be derived from the structure. The strained layer of Group III-V material can be, for example, a thin layer of In0.53Ga0.47As having a thickness in a range of about 2 nm to about 5 nm.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: April 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Cheng-Wei Cheng, Effendi Leobandung, Ning Li, Devendra K. Sadana, Kuen-Ting Shiu
  • Patent number: 10217632
    Abstract: A method of forming a semiconductor device is provided. The method includes depositing an aluminum-base interlayer on a silicon substrate, the aluminum-base interlayer having a thickness of less than about 100 nanometers; and growing a III-V compound material on the aluminum-base interlayer. The aluminum-base interlayer deposited directly on silicon allows for continuous and planar growth of III-V compound materials on the interlayer, which facilitates the manufacture of high quality electronic devices.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: February 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Cheng-Wei Cheng, Sanghoon Lee, Kuen-Ting Shiu
  • Patent number: 10141719
    Abstract: A structure includes an optoelectronic device having a Group IV substrate (e.g., Si); a buffer layer (e.g. SiGe) disposed on the substrate and a first distributed Bragg reflector (DBR) disposed on the buffer layer. The first DBR contains alternating layers of doped Group IV materials (e.g., alternating layers of SiyGe(1?y), where 0.8<y<1, and SizGe(1?z), where 0.2<z<0.4) that are substantially transparent to a wavelength of interest. The structure further includes a strained layer of a Group III-V material over the first DBR and a second DBR over the strained layer. The second DBR contains alternating layers of electrically conductive oxides (e.g., ITO/AZO) that are substantially transparent to the wavelength of interest. Embodiments of VCSELs and photodetectors can be derived from the structure. The strained layer of Group III-V material can be, for example, a thin layer of In0.53Ga0.47As having a thickness in a range of about 2 nm to about 5 nm.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: November 27, 2018
    Assignee: International Business Machines Corporation
    Inventors: Cheng-Wei Cheng, Effendi Leobandung, Ning Li, Devendra K. Sadana, Kuen-Ting Shiu
  • Patent number: 10135226
    Abstract: A structure includes an optoelectronic device having a Group IV substrate (e.g., Si); a buffer layer (e.g. SiGe) disposed on the substrate and a first distributed Bragg reflector (DBR) disposed on the buffer layer. The first DBR contains alternating layers of doped Group IV materials (e.g., alternating layers of SiyGe(1-y), where 0.8<y<1, and SizGe(1-z), where 0.2<z<0.4) that are substantially transparent to a wavelength of interest. The structure further includes a strained layer of a Group III-V material over the first DBR and a second DBR over the strained layer. The second DBR contains alternating layers of electrically conductive oxides (e.g., ITO/AZO) that are substantially transparent to the wavelength of interest. Embodiments of VCSELs and photodetectors can be derived from the structure. The strained layer of Group III-V material can be, for example, a thin layer of In0.53Ga0.47As having a thickness in a range of about 2 nm to about 5 nm.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: November 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Cheng-Wei Cheng, Effendi Leobandung, Ning Li, Devendra K. Sadana, Kuen-Ting Shiu
  • Patent number: 10122153
    Abstract: A structure includes an optoelectronic device having a Group IV substrate (e.g., Si); a buffer layer (e.g. SiGe) disposed on the substrate and a first distributed Bragg reflector (DBR) disposed on the buffer layer. The first DBR contains alternating layers of doped Group IV materials (e.g., alternating layers of SiyGe(1?y), where 0.8<y<1, and SizGe(1?z), where 0.2<z<0.4) that are substantially transparent to a wavelength of interest. The structure further includes a strained layer of a Group III-V material over the first DBR and a second DBR over the strained layer. The second DBR contains alternating layers of electrically conductive oxides (e.g., ITO/AZO) that are substantially transparent to the wavelength of interest. Embodiments of VCSELs and photodetectors can be derived from the structure. The strained layer of Group III-V material can be, for example, a thin layer of In0.53Ga0.47As having a thickness in a range of about 2 nm to about 5 nm.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: November 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: Cheng-Wei Cheng, Effendi Leobandung, Ning Li, Devendra K. Sadana, Kuen-Ting Shiu
  • Publication number: 20180226769
    Abstract: A structure includes an optoelectronic device having a Group IV substrate (e.g., Si); a buffer layer (e.g. SiGe) disposed on the substrate and a first distributed Bragg reflector (DBR) disposed on the buffer layer. The first DBR contains alternating layers of doped Group IV materials (e.g., alternating layers of SiyGe(1?y), where 0.8<y<1, and SizGe(1?z), where 0.2<z<0.4) that are substantially transparent to a wavelength of interest. The structure further includes a strained layer of a Group III-V material over the first DBR and a second DBR over the strained layer. The second DBR contains alternating layers of electrically conductive oxides (e.g., ITO/AZO) that are substantially transparent to the wavelength of interest. Embodiments of VCSELs and photodetectors can be derived from the structure. The strained layer of Group III-V material can be, for example, a thin layer of In0.53Ga0.47As having a thickness in a range of about 2 nm to about 5 nm.
    Type: Application
    Filed: March 27, 2018
    Publication date: August 9, 2018
    Inventors: Cheng-Wei Cheng, Effendi Leobandung, Ning Li, Devendra K. Sadana, Kuen-Ting Shiu
  • Patent number: 10043663
    Abstract: A heteroepitaxially grown structure includes a substrate and a mask including a high aspect ratio trench formed on the substrate. A cavity is formed in the substrate having a shape with one or more surfaces and including a resistive neck region at an opening to the trench. A heteroepitaxially grown material is formed on the substrate and includes a first region in or near the cavity and a second region outside the first region wherein the second region contains fewer defects than the first region.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: August 7, 2018
    Assignee: International Business Machines Corporation
    Inventors: Cheng-Wei Cheng, David L. Rath, Devendra K. Sadana, Kuen-Ting Shiu, Brent A. Wacaser
  • Publication number: 20180219355
    Abstract: A structure includes an optoelectronic device having a Group IV substrate (e.g., Si); a buffer layer (e.g. SiGe) disposed on the substrate and a first distributed Bragg reflector (DBR) disposed on the buffer layer. The first DBR contains alternating layers of doped Group IV materials (e.g., alternating layers of SiyGe(1-y), where 0.8<y<I, and SizGe(1-z), where 0.2<z<0.4) that are substantially transparent to a wavelength of interest. The structure further includes a strained layer of a Group III-V material over the first DBR and a second DBR over the strained layer. The second DBR contains alternating layers of electrically conductive oxides (e.g., ITO/AZO) that are substantially transparent to the wavelength of interest. Embodiments of VCSELs and photodetectors can be derived from the structure. The strained layer of Group III-V material can be, for example, a thin layer of In0.53Ga0.47As having a thickness in a range of about 2 nm to about 5 nm.
    Type: Application
    Filed: March 27, 2018
    Publication date: August 2, 2018
    Inventors: Cheng-Wei Cheng, Effendi Leobandung, Ning Li, Devendra K. Sadana, Kuen-Ting Shiu
  • Patent number: 10014377
    Abstract: An electrical device comprising a base semiconductor layer of a silicon including material; a dielectric layer present on the base semiconductor layer; a first III-V semiconductor material area present in a trench in the dielectric layer, wherein a via of the III-V semiconductor material extends from the trench through the dielectric layer into contact with the base semiconductor layer; a second III-V semiconductor material area present in the trench in the dielectric layer wherein the second III-V semiconductor material area does not have a via extending through the dielectric layer into contact with the base semiconductor layer; and a semiconductor device present on the second III-V semiconductor material area, wherein the first III-V semiconductor material area and the second III-V semiconductor material area are separated by a low aspect ratio trench extending to the dielectric layer.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: July 3, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Cheng-Wei Cheng, Edward William Kiewra, Amlan Majumdar, Devendra K. Sadana, Kuen-Ting Shiu, Yanning Sun
  • Patent number: 9984873
    Abstract: A method of forming a semiconducting material includes depositing a graded buffer on a substrate to form a graded layer of an indium (In) containing III-V material, the In containing III-V material being indium-gallium-arsenic (InGaAs) or indium-aluminum-arsenic (InAlAs) and comprising In in an increasing atomic gradient up to 35 atomic % (at. %) based on total atomic weight of InGa or InAl; and forming a layer of InGaAs on the graded layer, the layer of InGaAs comprising about 25 to about 100 at. % In based on total atomic weight of InGa.
    Type: Grant
    Filed: October 7, 2016
    Date of Patent: May 29, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Cheng-Wei Cheng, Devendra K. Sadana, Kuen-Ting Shiu, Yanning Sun
  • Patent number: 9966735
    Abstract: III-V lasers integrated with silicon photonic circuits and methods for making the same include a three-layer semiconductor stack formed from III-V semiconductors on a substrate, where a middle layer has a lower bandgap than a top layer and a bottom layer; a mirror region monolithically formed at a first end of the stack, configured to reflect emitted light in the direction of the stack; and a waveguide region monolithically formed at a second end of the stack, configured to transmit emitted light.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: May 8, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Cheng-Wei Cheng, Frank R. Libsch, Tak H. Ning, Uzma Rana, Kuen-Ting Shiu
  • Publication number: 20180069376
    Abstract: A structure includes an optoelectronic device having a Group IV substrate (e.g., Si); a buffer layer (e.g. SiGe) disposed on the substrate and a first distributed Bragg reflector (DBR) disposed on the buffer layer. The first DBR contains alternating layers of doped Group IV materials (e.g., alternating layers of SiyGe(1-y), where 0.8<y<1, and SizGe(1-z), where 0.2<z<0.4) that are substantially transparent to a wavelength of interest. The structure further includes a strained layer of a Group III-V material over the first DBR and a second DBR over the strained layer. The second DBR contains alternating layers of electrically conductive oxides (e.g., ITO/AZO) that are substantially transparent to the wavelength of interest. Embodiments of VCSELs and photodetectors can be derived from the structure. The strained layer of Group III-V material can be, for example, a thin layer of In0.53Ga0.47As having a thickness in a range of about 2 nm to about 5 nm.
    Type: Application
    Filed: November 13, 2017
    Publication date: March 8, 2018
    Inventors: Cheng-Wei Cheng, Effendi Leobandung, Ning Li, Devendra K. Sadana, Kuen-Ting Shiu