Abstract: In an embodiment of the present disclosure, an integrated circuit includes: a first interface suitable for receiving first to Nth data, where N is an even number equal to or greater than 2, and first to Nth multi-phase clocks; an interface conversion circuit suitable for generating serial data based on the first to Nth data that are received through the first interface, and generating a data strobe signal for strobing the serial data based on the first to Nth multi-phase clocks that are received through the first interface; and a second interface suitable for receiving the serial data and the data strobe signal.

Abstract: Disclosed are a bus inversion encoder module that utilizes future data in a data bus including a serializer with minimum latency and high transition reduction efficiency by comparing current data with both past data and the future data and encoding the current data, and a bus inversion system including the same. The bus inversion encoder module uses current data, past data, and future data transmitted through a bus and each including a plurality of bits, determines whether to invert the current data, and generates a current flag and coded current data by using whether to invert, an output flag, and the current data. The output flag is generated by summing the current flag and the coded current data and serially converting the current flag and the coded current data.

Abstract: Disclosed is a memory device including an error logic unit suitable for determining whether an error is present in command signals to generate a command error signal; a replica delay circuit suitable for replicating a delay value of the error logic unit and generating an input strobe signal by delaying a strobe signal of the command signals; an output strobe signal generation circuit suitable for generating an output strobe signal activated after a command error latency elapses from a time point at which the command signals are received; and a pipe circuit suitable for receiving and storing the command error signal in response to the input strobe signal and outputting the stored command error signal in response to the output strobe signal.

Abstract: In an embodiment of the present disclosure, an integrated circuit includes: a first interface suitable for receiving first to Nth data, where N is an even number equal to or greater than 2, and first to Nth multi-phase clocks; an interface conversion circuit suitable for generating serial data based on the first to Nth data that are received through the first interface, and generating a data strobe signal for strobing the serial data based on the first to Nth multi-phase clocks that are received through the first interface; and a second interface suitable for receiving the serial data and the data strobe signal.

Abstract: A clock generator circuit includes: first to Nth nodes, where N is an even number equal to or greater than 2; and a parallel-to-serial conversion circuit suitable for parallel-to-serial converting signals of the first to Nth nodes to output a clock through an output node, wherein, in an activation section of the clock, the signals of even-numbered nodes among the first to Nth nodes have a first level, and the signals of odd-numbered nodes among the first to Nth nodes have a second level which is different from the first level, and wherein, in a deactivation section of the clock, the signals of the first to Nth nodes have the same level.

Abstract: A delay circuit includes a first delay line suitable for delaying a first clock by a delay value that is adjusted based on a delay control code; a delay control circuit suitable for comparing a phase of the first clock delayed through the first delay line with a phase of a second clock to generate the delay control code; and a second delay line having, based on a delay control code, a delay value corresponding to a half of the delay value of the first delay line.

Abstract: Disclosed is a memory device including an error logic unit suitable for determining whether an error is present in command signals to generate a command error signal; a replica delay circuit suitable for replicating a delay value of the error logic unit and generating an input strobe signal by delaying a strobe signal of the command signals; an output strobe signal generation circuit suitable for generating an output strobe signal activated after a command error latency elapses from a time point at which the command signals are received; and a pipe circuit suitable for receiving and storing the command error signal in response to the input strobe signal and outputting the stored command error signal in response to the output strobe signal.

Abstract: A clock generator circuit includes: first to Nth nodes, where N is an even number equal to or greater than 2; and a parallel-to-serial conversion circuit suitable for parallel-to-serial converting signals of the first to Nth nodes to output a clock through an output node, wherein, in an activation section of the clock, the signals of even-numbered nodes among the first to Nth nodes have a first level, and the signals of odd-numbered nodes among the first to Nth nodes have a second level which is different from the first level, and wherein, in a deactivation section of the clock, the signals of the first to Nth nodes have the same level.

Abstract: A delay circuit includes a first delay line suitable for delaying a first clock by a delay value that is adjusted based on a delay control code; a delay control circuit suitable for comparing a phase of the first clock delayed through the first delay line with a phase of a second clock to generate the delay control code; and a second delay line having, based on a delay control code, a delay value corresponding to a half of the delay value of the first delay line.

Abstract: A semiconductor device includes a latch control circuit configured to generate a latch input signal, which is enabled in response to a latency signal, and configured to generate a latch output signal, which is enabled in response to an order control signal. The semiconductor device also includes a pipe latch circuit configured to latch input data in response to a pipe input signal and configured to output the latched input data as latch data in response to a pipe output signal. The semiconductor device additionally includes a data output circuit configured to latch the latch data in response to the latch input signal and configured to output the latched latch data as output data in response to the latch output signal, wherein the output data is outputted by performing an alignment operation for the latch data in response to the latch output signal.

Abstract: Provided is a removable storage system including: a data storage device configured to store a plurality of files including a first file and a second file; a host interface configured to receive, from a host, a pattern matching request including pattern information and file information regarding the plurality of files, and transmit, to the host, a result of pattern matching regarding the plurality of files; and a pattern matching accelerator configured to perform the pattern matching in response to the pattern matching request, wherein the pattern matching accelerator includes a scan engine configured to scan data based on a pattern, and a scheduler configured to control the scan engine to stop scanning the first file and start scanning the second file.

Abstract: A semiconductor device includes a read mode signal generation circuit and a read alignment circuit. The read mode signal generation circuit compares a read command with at least one of internal clock signal to generate a read mode signal. The read alignment circuit is synchronized with the at least one internal clock signal to generate read data in response to internal data. The read alignment circuit controls an alignment sequence of the internal data in response to the read mode signal.

Abstract: A semiconductor device includes a read mode signal generation circuit and a read alignment circuit. The read mode signal generation circuit compares a read command with at least one of internal clock signal to generate a read mode signal. The read alignment circuit is synchronized with the at least one internal clock signal to generate read data in response to internal data. The read alignment circuit controls an alignment sequence of the internal data in response to the read mode signal.

Abstract: A semiconductor device includes a latch control circuit configured to generate a latch input signal, which is enabled in response to a latency signal, and configured to generate a latch output signal, which is enabled in response to an order control signal. The semiconductor device also includes a pipe latch circuit configured to latch input data in response to a pipe input signal and configured to output the latched input data as latch data in response to a pipe output signal. The semiconductor device additionally includes a data output circuit configured to latch the latch data in response to the latch input signal and configured to output the latched latch data as output data in response to the latch output signal, wherein the output data is outputted by performing an alignment operation for the latch data in response to the latch output signal.

Abstract: A semiconductor device includes a read mode signal generation circuit and a read alignment circuit. The read mode signal generation circuit compares a read command with at least one of internal clock signal to generate a read mode signal. The read alignment circuit is synchronized with the at least one internal clock signal to generate read data in response to internal data. The read alignment circuit controls an alignment sequence of the internal data in response to the read mode signal.

Abstract: Provided is a removable storage system including: a data storage device configured to store a plurality of files including a first file and a second file; a host interface configured to receive, from a host, a pattern matching request including pattern information and file information regarding the plurality of files, and transmit, to the host, a result of pattern matching regarding the plurality of files; and a pattern matching accelerator configured to perform the pattern matching in response to the pattern matching request, wherein the pattern matching accelerator includes a scan engine configured to scan data based on a pattern, and a scheduler configured to control the scan engine to stop scanning the first file and start scanning the second file.

Abstract: A semiconductor device includes a read mode signal generation circuit and a read alignment circuit. The read mode signal generation circuit compares a read command with at least one of internal clock signal to generate a read mode signal. The read alignment circuit is synchronized with the at least one internal clock signal to generate read data in response to internal data. The read alignment circuit controls an alignment sequence of the internal data in response to the read mode signal.

Abstract: An integrated circuit including semiconductor devices may be provided. The semiconductor device may be configured to compare phases of strobe signals which are generated according to internal delay times of the semiconductor devices and configured to control points of time that an internal command is inputted to the internal circuits of the semiconductor devices according to a comparison result of the phases of the strobe signals.

Abstract: An integrated circuit including semiconductor devices may be provided. The semiconductor device may be configured to compare phases of strobe signals which are generated according to internal delay times of the semiconductor devices and configured to control points of time that an internal command is inputted to the internal circuits of the semiconductor devices according to a comparison result of the phases of the strobe signals.

Abstract: A semiconductor may include a core block configured to store and output data, and may be configured to output internal information. The semiconductor may include a through via configured for signal transfer with another semiconductor chip. The semiconductor may include an internal information processing circuit configured to transmit internal information selected from the internal information to the through via, or may be configured to output internal information of the other semiconductor chip, which has been transmitted through the through via, to an exterior through a special purpose pin, in response to test signals.