Patents by Inventor Kumiko Konishi

Kumiko Konishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10692860
    Abstract: An object of the present invention is to increase the reliability of a power module and a power converter and to extend their life. In order to achieve this, a power module includes: two switching devices each including a diode and a transistor, the two switching devices being electrically connected in parallel; and an insulating substrate on which the two switching devices are mounted. Further, a gate electrode of MOFET that each of the two switching device has is electrically connected to a gate resistance. Further, of the two switching devices, the gate resistance that is electrically connected to the switching device, whose current value is smaller when a predetermined voltage is applied in the forward direction of the body diode, is greater than the gate resistance that is electrically connected to the switching device whose current value is larger.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: June 23, 2020
    Assignee: HITACHI, LTD.
    Inventors: Ryuusei Fujita, Kumiko Konishi, Akio Shima
  • Publication number: 20200006066
    Abstract: In a silicon carbide stacked substrate, the efficiency of converting the basal plane dislocation (BPD) which is a fault to deteriorate the current-carrying reliability into a threading edge dislocation (TED) which is a harmless fault is improved, thereby improving the reliability of the silicon carbide stacked substrate. As means therefor, in a silicon carbide stacked substrate including a SiC substrate and a buffer layer and a drift layer which are epitaxial layers sequentially formed on the SiC substrate, a semiconductor layer having an impurity concentration lower than those of the SiC substrate and the buffer layer and higher than that of the drift layer is formed between the SiC substrate and the buffer layer so as to be in contact with an upper surface of the SiC substrate.
    Type: Application
    Filed: January 30, 2018
    Publication date: January 2, 2020
    Inventors: Kumiko KONISHI, Kiyoshi OOUCHI, Keisuke KOBAYASHI, Akio SHIMA
  • Patent number: 10367090
    Abstract: Provided is a silicon carbide semiconductor device in which SiC-MOSFETs are formed within an active region of an n-type silicon carbide semiconductor substrate, and a p+-type semiconductor region is formed on an upper surface of an epitaxial layer so as to surround the active region.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: July 30, 2019
    Assignee: Hitachi, Ltd.
    Inventors: Kumiko Konishi, Ryuusei Fujita, Kazuki Tani, Akio Shima
  • Publication number: 20190198495
    Abstract: An object of the present invention is to increase the reliability of a power module and a power converter and to extend their life. In order to achieve this, a power module includes: two switching devices each including a diode and a transistor, the two switching devices being electrically connected in parallel; and an insulating substrate on which the two switching devices are mounted. Further, a gate electrode of MOFET that each of the two switching device has is electrically connected to a gate resistance. Further, of the two switching devices, the gate resistance that is electrically connected to the switching device, whose current value is smaller when a predetermined voltage is applied in the forward direction of the body diode, is greater than the gate resistance that is electrically connected to the switching device whose current value is larger.
    Type: Application
    Filed: December 12, 2018
    Publication date: June 27, 2019
    Inventors: Ryuusei FUJITA, Kumiko KONISHI, Akio SHIMA
  • Publication number: 20190115465
    Abstract: Provided is a silicon carbide semiconductor device in which SiC-MOSFETs are formed within an active region of an n-type silicon carbide semiconductor substrate, and a p+-type semiconductor region is formed on an upper surface of an epitaxial layer so as to surround the active region.
    Type: Application
    Filed: July 2, 2018
    Publication date: April 18, 2019
    Applicant: HITACHI, LTD.
    Inventors: Kumiko KONISHI, Ryuusei FUJITA, Kazuki TANI, Akio SHIMA
  • Patent number: 9159562
    Abstract: A Schottky junction type semiconductor device in which the opening width of a trench can be decreased without deteriorating the withstanding voltage. The cross sectional shape of a trench has a shape of a sub-trench in which the central portion is higher and the periphery is lower at the bottom of the trench, and a p type impurity is introduced vertically to the surface of the drift layer thereby forming a p+ SiC region, which is formed in contact to the inner wall of the trench having the sub-trench disposed therein, such that the junction position is formed more deeply in the periphery of the bottom of the trench than the junction position in the central portion of the bottom of the trench.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: October 13, 2015
    Assignee: Hitachi, Ltd.
    Inventors: Kumiko Konishi, Natsuki Yokoyama, Norifumi Kameshiro
  • Patent number: 9054174
    Abstract: In a MOSFET using a SiC substrate, a source region having low resistance and high injection efficiency is formed without performing a high-temperature heat treatment. A vertical Schottky barrier transistor in which a source region SR on a SiC epitaxial substrate is constituted by a metal material is formed. The source region SR composed of a metal material can be brought into a low resistance state without performing a high-temperature activation treatment. Further, by segregating a conductive impurity DP at an interface between the source region SR composed of a metal material and the SiC epitaxial substrate, the Schottky barrier height can be reduced, and the carrier injection efficiency from the source region SR can be improved.
    Type: Grant
    Filed: June 7, 2013
    Date of Patent: June 9, 2015
    Assignee: Hitachi, Ltd.
    Inventors: Digh Hisamoto, Naoki Tega, Kumiko Konishi, Hiroyuki Matsushima
  • Publication number: 20130328062
    Abstract: In a MOSFET using a SiC substrate, a source region having low resistance and high injection efficiency is formed without performing a high-temperature heat treatment. A vertical Schottky barrier transistor in which a source region SR on a SiC epitaxial substrate is constituted by a metal material is formed. The source region SR composed of a metal material can be brought into a low resistance state without performing a high-temperature activation treatment. Further, by segregating a conductive impurity DP at an interface between the source region SR composed of a metal material and the SiC epitaxial substrate, the Schottky barrier height can be reduced, and the carrier injection efficiency from the source region SR can be improved.
    Type: Application
    Filed: June 7, 2013
    Publication date: December 12, 2013
    Inventors: Digh Hisamoto, Naoki Tega, Kumiko Konishi, Hiroyuki Matsushima