Patents by Inventor Kumiko Nomura

Kumiko Nomura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11901568
    Abstract: To provide an electrocatalyst for fuel cells, which is configured to ensure both the initial performance and durability of fuel cells. An electrocatalyst for fuel cells, wherein the electrocatalyst comprises a carbon support including a mesopore and a catalyst alloy supported on the carbon support, and the catalyst alloy is a catalyst alloy of platinum and a transition metal; wherein the mesopore includes at least one throat; wherein an average effective diameter of the at least one throat is 1.8 nm or more and less than 3.2 nm; and wherein a transition metal ratio of the catalyst alloy supported on a deeper-side region than the at least one throat, is lower than the transition metal ratio of the catalyst alloy supported on a nearer-side region than the at least one throat.
    Type: Grant
    Filed: March 3, 2022
    Date of Patent: February 13, 2024
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, CATALER CORPORATION
    Inventors: Ryo Shimizu, Kumiko Nomura, Tomohiro Takeshita, Shu Miyasaka, Kenji Yamamoto
  • Patent number: 11893476
    Abstract: According to an embodiment, an inference system includes a recurrent neural network circuit, an inference neural network, and a control circuit. The recurrent neural network circuit receives M input signals and outputs N intermediate signals, where M is an integer of 2 or more and N is an integer of 2 or more. The inference neural network circuit receives the N intermediate signals and outputs L output signals, where L is an integer of 2 or more. The control circuit adjusts a plurality of coefficients that are set to the recurrent neural network circuit and adjusts a plurality of coefficients that are set to the inference neural network circuit. The control circuit adjusts the coefficients set to the recurrent neural network circuit according to a total delay time period from timing for applying the M input signals until timing for firing the L output signals.
    Type: Grant
    Filed: November 2, 2022
    Date of Patent: February 6, 2024
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takao Marukame, Kumiko Nomura, Yoshifumi Nishi, Koichi Mizushima
  • Publication number: 20240006619
    Abstract: The present embodiment is a catalyst for a fuel cell including: a catalyst metal; and a carrier that supports the catalyst metal, in which an outer surface area of the carrier to an inner surface area of the carrier, which is a ratio between the inner and outer surface areas of the carrier, is 0.56 to 0.69, and a proportion of the catalyst metal supported on an outer surface of the carrier is 23% to 35%.
    Type: Application
    Filed: June 14, 2023
    Publication date: January 4, 2024
    Inventors: Kumiko NOMURA, Rui IMOTO, Hidetoshi OKADA, Naoki HASEGAWA, Tomohiro TAKESHITA, Kazuhisa YANO, Kenji YAMAMOTO, Yuko MATSUMURA, Yuuki KASAMA
  • Publication number: 20230343971
    Abstract: To provide a carbon support for catalysts for fuel cells, which increases the power generation performance of fuel cells, a catalyst for fuel cells, a catalyst layer for fuel cells, and a method for producing the carbon support. A carbon support for catalysts for fuel cells, wherein the carbon support includes at least one pore; wherein a thickness of a carbon wall of the carbon support, which is derived from a three-dimensional pore structure of a silica mold obtained by pore volume measurement of the silica mold by nitrogen adsorption analysis, is 3.3 nm or more and 11.2 nm or less; and wherein a carbon wall content is more than 60.3 ml/g and less than 190.8 ml/g.
    Type: Application
    Filed: April 20, 2023
    Publication date: October 26, 2023
    Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, CATALER CORPORATION
    Inventors: Yunan WANG, Rui IMOTO, Kumiko NOMURA, Naoki HASEGAWA, Tomohiro TAKESHITA, Kazuhisa YANO, Hironobu NANBU, Yuuki KASAMA, Keisuke ASAKURA, Takanobu KUROKI, Hitohiko SATO, Tsubasa YONEUCHI, Akihiro HORI
  • Patent number: 11777006
    Abstract: In a gate electrode of a nonvolatile memory device of an embodiment, a tunnel insulating film covers a channel region. A first current collector file is disposed on the side opposite to the channel region with respect to the tunnel insulating film. An ion conductor film is disposed between the tunnel insulating film and the first current collector film. A first electrode film is disposed between the tunnel insulating film and the ion conductor film. The first electrode film is in contact with the ion conductor film. A second electrode film is disposed between the ion conductor film and the first current collector film. The second electrode film is in contact with the ion conductor film. A second current collector film is disposed between the tunnel insulating film and the second electrode film.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: October 3, 2023
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichi Mizushima, Takao Marukame, Yoshifumi Nishi, Kumiko Nomura
  • Publication number: 20230305806
    Abstract: A multiplication device according to one embodiment includes a short-term memory circuit, a long-term memory circuit, a conversion circuit, and a control circuit. The short-term memory circuit generates a first control voltage in accordance with a weight value. The long-term memory circuit generates a second control voltage by a circuit with a larger time constant than the short-term memory circuit. The conversion circuit outputs an output current by multiplying an input voltage by a conductance. The output current is output by that, the first control voltage is applied to a control terminal of the conversion circuit, and an input voltage according to an input value is applied to an input terminal of the conversion circuit. The control circuit executes a calibration process of matching the first control voltage with the second control voltage by transferring an electric charge from the long-term memory circuit to the short-term memory circuit.
    Type: Application
    Filed: August 16, 2022
    Publication date: September 28, 2023
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takao MARUKAME, Koichi MIZUSHIMA, Yoshifumi NISHI, Kumiko NOMURA
  • Publication number: 20230299308
    Abstract: Mesoporous carbon includes a linked structure in which carbon particles are linked. The carbon particles have primary pores and are primary particles. An average entrance diameter of the primary pores is 2.0 nm or more and 3.0 nm or less. An average constriction diameter of the primary pores is 1.6 nm or more and 2.4 nm or less. An electrode catalyst for a fuel cell includes the mesoporous carbon and catalyst particles supported in the primary pores of the mesoporous carbon. A catalyst layer includes the electrode catalyst for a fuel cell and a catalyst layer ionomer.
    Type: Application
    Filed: March 13, 2023
    Publication date: September 21, 2023
    Inventors: Naoki HASEGAWA, Kazuhisa YANO, Tomohiro TAKESHITA, Rui IMOTO, Kumiko NOMURA, Yunan WANG, Yuko MATSUMURA, Yuuki KASAMA
  • Publication number: 20230289581
    Abstract: According to an embodiment, an inference system includes a recurrent neural network circuit, an inference neural network, and a control circuit. The recurrent neural network circuit receives M input signals and outputs N intermediate signals, where M is an integer of 2 or more and N is an integer of 2 or more. The inference neural network circuit receives the N intermediate signals and outputs L output signals, where L is an integer of 2 or more. The control circuit adjusts a plurality of coefficients that are set to the recurrent neural network circuit and adjusts a plurality of coefficients that are set to the inference neural network circuit. The control circuit adjusts the coefficients set to the recurrent neural network circuit according to a total delay time period from timing for applying the M input signals until timing for firing the L output signals.
    Type: Application
    Filed: November 2, 2022
    Publication date: September 14, 2023
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takao MARUKAME, Kumiko NOMURA, Yoshifumi NISHI, Koichi MIZUSHIMA
  • Publication number: 20230289579
    Abstract: A neural network apparatus according to an embodiment includes neuron circuits, synaptic circuits, and a control circuit. A firing circuit of each neuron circuit outputs a firing signal when absolute value of the internal potential is larger than a firing threshold. A firing threshold adjustment circuit of each neuron circuit changes the firing threshold in accordance with frequency of the firing signal. When the firing signal is output from a pre-synaptic neuron circuit, the synaptic circuit changes the synaptic weight in accordance with a contrast between a learning threshold and the absolute value of the internal potential held in a post-synaptic neuron circuit. The control circuit changes the learning threshold in accordance with frequency of the firing signal from a target neuron circuit. The learning threshold is used for changing the synaptic weight stored in one or more synaptic circuits each outputting the output signal to the target neuron.
    Type: Application
    Filed: August 31, 2022
    Publication date: September 14, 2023
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kumiko NOMURA, Yoshifumi NISHI, Takao MARUKAME, Koichi MIZUSHIMA
  • Patent number: 11651193
    Abstract: According to an embodiment, an operation apparatus includes a first neural network, a second neural network, an evaluation circuit, and a coefficient-updating circuit. The first neural network performs an operation in a first mode. The second neural network performs an operation in a second mode and has a same layer structure as the first neural network. The evaluation circuit evaluates an error of the operation of the first neural network in the first mode and evaluates an error of the operation of the second neural network in the second mode. The coefficient-updating circuit updates, in the first mode, coefficients set for the second neural network based on an evaluating result of the error of the operation of the first neural network, and updates, in the second mode, coefficients set for the first neural network based on an evaluating result of the error of the operation of the second neural network.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: May 16, 2023
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takao Marukame, Yoshifumi Nishi, Kumiko Nomura
  • Patent number: 11636315
    Abstract: According to an embodiment, a synapse circuit includes: a buffer that changes an output signal to a second logical value at a timing when an input signal exceeds a first threshold level, in a case where the output signal has a first logical value in a first mode, and changes the output signal to the second logical value at a timing when the input signal exceeds a reference level lower than the first threshold level, in a case where the output signal has the first logical value in a second mode; an adjusting unit that adjusts the first threshold level depending on a stored coefficient; and a mode switching unit that operates the buffer in the first mode during a period in which an acquired spike is not generated, and operates the buffer in the second mode during a period in which the spike is generated.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: April 25, 2023
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takao Marukame, Kumiko Nomura, Yoshifumi Nishi
  • Patent number: 11625579
    Abstract: A spiking neural network device according to an embodiment includes a synaptic element, a neuron circuit, a synaptic potentiator, and a synaptic depressor. The synaptic element has a variable weight. The neuron circuit inputs a spike voltage having a magnitude adjusted in accordance with the weight of the synaptic element via the synaptic element, and fires when a predetermined condition is satisfied. The synaptic potentiator performs a potentiating operation for potentiating the weight of the synaptic element depending on input timing of the spike voltage and firing timing of the neuron circuit. The synaptic depressor performs a depression operation for depressing the weight of the synaptic element in accordance with a schedule independent from the input timing of the spike voltage and the firing timing of the neuron circuit.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: April 11, 2023
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshifumi Nishi, Kumiko Nomura, Radu Berdan, Takao Marukame
  • Patent number: 11620501
    Abstract: According to an embodiment, a neural network apparatus includes cores, routers, a tree path, and a short-cut path. The cores are provided according to leaves in a tree structure, each core serving as a circuit that performs calculation or processing for part of elements of the neural network. The routers are provided according to nodes other than the leaves in the tree structure. The tree path connects the cores and the routers such that data is transferred along the tree structure. The short-cut path connects part of the routers such that data is transferred on a route differing from the tree path. The routers transmit data output from each core to any of the cores serving as a transmission destination on one of routes in the tree path and the short-cut path such that the calculation or the processing is performed according to a structure of the neural network.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: April 4, 2023
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kumiko Nomura, Takao Marukame, Yoshifumi Nishi
  • Publication number: 20230079071
    Abstract: A variable resistance element according to an embodiment serves to change to a low resistance state or a high resistance state. The variable resistance element includes a first transition metal compound layer, a second transition metal compound layer, and a lithium ion conductor layer. The first transition metal compound layer is connected to a first electrode. The first transition metal compound layer is a metal compound containing lithium ions in lattice interstices. The second transition metal compound layer is connected to a second electrode. The second transition metal compound layer is a metal compound containing lithium ions in lattice interstices. The lithium ion conductor layer is provided between the first transition metal compound layer and the second transition metal compound layer. The lithium ion conductor layer is a solid substance that is permeable to lithium ions and is less permeable to electrons.
    Type: Application
    Filed: August 19, 2022
    Publication date: March 16, 2023
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takao MARUKAME, Koichi MIZUSHIMA, Yoshifumi NISHI, Kumiko NOMURA
  • Publication number: 20230058490
    Abstract: A synaptic circuit according to an embodiment includes a weight storage circuit and a transmission circuit. The weight storage circuit stores a synaptic weight indicating a first value or a second value. The transmission circuit receives a firing signal output from a pre-synaptic neuron circuit, and supplies an output signal to a post-synaptic neuron circuit. The output signal is obtained by adding, to the firing signal, influence of the synaptic weight. The post-synaptic neuron circuit holds an internal potential. When the firing signal is received, the weight storage circuit causes the synaptic weight to change to indicate the first or second value with a first probability in accordance with a comparison result between the internal potential and a set potential. The weight storage circuit causes the synaptic weight to change to indicate the first value with a second probability regardless of whether or not the firing signal is received.
    Type: Application
    Filed: March 7, 2022
    Publication date: February 23, 2023
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kumiko Nomura, Yoshifumi Nishi, Takao Marukame, Koichi Mizushima
  • Patent number: 11586897
    Abstract: According to an embodiment, a reinforcement learning system includes a memristor array in which each of a plurality of first direction lines corresponds to one of a plurality of states, and each of a plurality of second direction lines corresponds to one of a plurality of actions, a first voltage application unit that individually applies voltage to the first direction lines, a second voltage application unit that individually applies voltage to the second direction lines, a action decision circuit that decides action to be selected by an agent in a state corresponding to a first direction line to which a readout voltage is applied, a action storage unit that stores action selected by the agent in each state that can be caused in an environment, and a trace storage unit that stores a time at which the state is caused by action selected by the agent.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: February 21, 2023
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshifumi Nishi, Radu Berdan, Takao Marukame, Kumiko Nomura
  • Patent number: 11586887
    Abstract: According to an embodiment, a neural network apparatus includes a plurality of neuron circuits, each including an integration circuit, a firing circuit, and a secondary battery. The integration circuit is configured to output an integral signal obtained by integrating input signals. The firing circuit is configured to generate, in accordance with the integral signal, a pulse signal to be transmitted to the neuron circuit provided at a subsequent layer. The secondary battery is configured to supply the firing circuit with drive electric power used for generating the pulse signal.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: February 21, 2023
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takao Marukame, Tetsufumi Tanamoto, Yoshifumi Nishi, Kumiko Nomura
  • Patent number: 11526738
    Abstract: According to an embodiment, an inference system includes a recurrent neural network circuit, an inference neural network, and a control circuit. The recurrent neural network circuit receives M input signals and outputs N intermediate signals, where M is an integer of 2 or more and N is an integer of 2 or more. The inference neural network circuit receives the N intermediate signals and outputs L output signals, where L is an integer of 2 or more. The control circuit adjusts a plurality of coefficients that are set to the recurrent neural network circuit and adjusts a plurality of coefficients that are set to the inference neural network circuit. The control circuit adjusts the coefficients set to the recurrent neural network circuit according to a total delay time period from timing for applying the M input signals until timing for firing the L output signals.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: December 13, 2022
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takao Marukame, Kumiko Nomura, Yoshifumi Nishi, Koichi Mizushima
  • Publication number: 20220320528
    Abstract: Mesoporous carbon has a connecting structure in which primary particles made of carbon particles having primary pores with a primary pore diameter of less than 20 nm are connected. In the mesoporous carbon, the pore capacity of secondary pores with secondary pore diameters within a range of 20 nm to 100 nm, which is measured by a mercury intrusion method, is 0.42 cm3/g or more and 1.34 cm3/g or less. In addition, the mesoporous carbon has a linearity of 2.2 or more and 2.6 or less. An electrode catalyst for a fuel cell includes the mesoporous carbon and catalyst particles supported in the primary pores in the mesoporous carbon. Furthermore, a catalyst layer includes the electrode catalyst for the fuel cell and a catalyst layer ionomer.
    Type: Application
    Filed: March 28, 2022
    Publication date: October 6, 2022
    Inventors: Naoki HASEGAWA, Kazuhisa YANO, Tomohiro TAKESHITA, Rui IMOTO, Kumiko NOMURA, Noriyuki KITAO, Yunan WANG, Yuuki KASAMA
  • Patent number: 11461617
    Abstract: According to an embodiment, a neural network device includes a plurality of cores, and a plurality of routers. Each of the plurality of routers includes an input circuit and an output circuit. Each of the plurality of cores transmits at least one of forward direction data propagating in the neural network in a forward direction and reverse direction data propagating in the neural network in a reverse direction. The input circuit receives the forward direction data and the reverse direction data from any one of the plurality of cores and the plurality of routers. The output circuit or the input circuit selectively deletes the reverse direction data stored based on a request signal for requesting reception of data.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: October 4, 2022
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kumiko Nomura, Takao Marukame