Abstract: According to one embodiment, a decoding device comprises a converter configured to convert read data to first likelihood information by using a first conversion table, a decoder which decodes the first likelihood information, a controller which outputs a decoding result of the decoder when the decoder succeeds decoding, and a creator module which creates a second conversion table based on the decoding result when the decoder fails decoding. When the second conversion table is created, at least a part of the decoding result is converted to second likelihood information by using the second conversion table the second likelihood information is decoded.

Abstract: According to one embodiment, a decoding device comprises a converter configured to convert read data to first likelihood information by using a first conversion table, a decoder which decodes the first likelihood information, a controller which outputs a decoding result of the decoder when the decoder succeeds decoding, and a creator module which creates a second conversion table based on the decoding result when the decoder fails decoding. When the second conversion table is created, at least a part of the decoding result is converted to second likelihood information by using the second conversion table the second likelihood information is decoded.

Abstract: A memory system according to an embodiment includes a semiconductor memory and a memory controller. The semiconductor memory includes memory cells and a sequencer. Each of the memory cells stores first data when it has a first threshold voltage, and stores second data when it has a second threshold voltage. The sequencer performs a first write operation for write data. In the first write operation, the sequencer executes a program loop repeatedly and terminates the first write operation, when the verify operation for the first data has passed and the verify operation for the second data has not passed. The sequencer performs a second write operation for the write data based on a first command from the memory controller after the first write operation is terminated.

Abstract: A memory system according to an embodiment includes a semiconductor memory and a memory controller. The semiconductor memory includes memory cells and a sequencer. Each of the memory cells stores first data when it has a first threshold voltage, and stores second data when it has a second threshold voltage. The sequencer performs a first write operation for write data. In the first write operation, the sequencer executes a program loop repeatedly and terminates the first write operation, when the verify operation for the first data has passed and the verify operation for the second data has not passed. The sequencer performs a second write operation for the write data based on a first command from the memory controller after the first write operation is terminated.